EPM9560RC208-12 vs EPM9560RC208-10N 比較
詳細並排比較 EPM9560RC208-12 由 Altera 與 EPM9560RC208-10N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-12 | EPM9560RC208-10N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | — |
| Macrocells | 560 | — |
| Flip-Flops | 772 | — |
| Usable Gates | 12000 | 12,000 |
| User I/O Lines | 153 | — |
| Propagation Delay (tPD) | 12 ns | — |
| 最大時脈頻率 | 125 MHz | — |
| Supply Voltage (VCCINT) | 5 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| 封裝 | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (Power Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Logic Array Blocks | 20 | — |
| Speed Grade | -12 (12 ns) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device | — | EPM9560 |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 153 |
| Pin-to-Pin Delay (tPD1) | — | 10 ns |
| I/O Bank Voltage (VCCIO) | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-system via IEEE 1149.1 JTAG |