EPM9560RC208-15C vs EPM9560RC208-13 比較
詳細並排比較 EPM9560RC208-15C 由 Altera 與 EPM9560RC208-13 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-15C | EPM9560RC208-13 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | EEPROM-based CPLD (EPLD) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| User I/O Pins | 149 | 208 |
| Propagation Delay (tPD) | 15 ns | 13 ns |
| Maximum Counter Frequency | 117.6 MHz | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| 封裝 | 208-pin RQFP | 208-pin RQFP (Power Quad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度範圍 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Speed Grade | -15 (15 ns) | -13 (13 ns pin-to-pin) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Architecture | Multiple Array MatriX (MAX) third generation | — |
| Device Family | — | MAX 9000 EPLD |
| Logic Array Blocks (LABs) | — | 20 |
| Package Code | — | RC208 |
| 最大時脈頻率 | — | 125 MHz |
| 供應電壓 | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |