EPM9560RC208-20N vs EPM9560WC208-20 比較
詳細並排比較 EPM9560RC208-20N 由 Intel 與 EPM9560WC208-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 Obsolete規格比較
| 參數 | EPM9560RC208-20N | EPM9560WC208-20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 (EPM9560) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | — |
| Propagation Delay (tPD) | 20 ns | — |
| 封裝 | 208-pin RQFP (PowerQuad Flat Pack) | PQFP-208 (RQFP/WQFP) |
| User I/O Pins | 149 | 149 |
| 供應電壓 | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes, JTAG BST (IEEE 1149.1) |
| JTAG Interface | IEEE Std. 1149.1 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] |
| RoHS 狀態 | Lead-free (N suffix) | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | — |
| Flip-Flops | 772 (per EPM9560 series data) | — |
| Speed Grade | -20 (20 ns) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | [DATA_NEEDED] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (EPLD) |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum Propagation Delay (tPD) | — | 23.6 ns |
| Process Technology | — | CMOS, EEPROM-based |
| Supply Voltage (VCCINT) | — | 5 V (typical, see datasheet) |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (multi-voltage I/O) |
| Pin/Package Suffix | — | W = power PQFP; -20 = 23.6 ns speed grade |
| Lead-Free | — | [DATA_NEEDED] |
| 無鹵素 | — | [DATA_NEEDED] |