EPM9560RC208-3 vs EPM9560RC208-12 比較
詳細並排比較 EPM9560RC208-3 由 Altera 與 EPM9560RC208-12 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-3 | EPM9560RC208-12 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EEPROM-based CPLD |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 12,000 | 12000 |
| Maximum Operating Frequency | [DATA_NEEDED: f_MAX] | — |
| Pin-to-Pin Delay (speed grade -3) | approximately 3 ns (slowest grade) | — |
| Speed Grade | -3 | -12 (12 ns) |
| 封裝 | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (S-PQFP-G208) |
| I/O Voltage Tolerance | 5V | — |
| Process Technology | 0.5 µm CMOS EPROM | — |
| Programming Interface | ByteBlaster / BitBlaster (JTAG-compatible) | — |
| 工作溫度 | [DATA_NEEDED: industrial / commercial range] | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Lifecycle | Mature / Last-time-buy (per Altera PDN for selected MAX 9000 ordering codes) | — |
| Flip-Flops | — | 772 |
| User I/O Lines | — | 153 |
| Propagation Delay (tPD) | — | 12 ns |
| 最大時脈頻率 | — | 125 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.50 mm |
| 安裝類型 | — | Surface Mount |
| Configuration Memory | — | EEPROM (non-volatile) |
| Logic Array Blocks | — | 20 |