EPM9560RC240-15 vs EPM9560RC240-15N 比較

詳細並排比較 EPM9560RC240-15 由 Intel 與 EPM9560RC240-15N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM9560RC240-15 EPM9560RC240-15N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Logic Family MAX 9000 (CMOS EEPROM-based) CMOS (EEPROM-based)
Macrocells 560 560
Usable Gates 12,000 12,000
User I/O Pins 191 —
封裝 240-pin RQFP (32x32 mm) with exposed pad RQFP-240 (240-pin Plastic Quad Flat Pack)
Pin-to-Pin Propagation Delay 15 ns —
Maximum Internal Frequency 145 MHz —
供應電壓 5.0 V 5.0 V
工作溫度 0 C to 70 C (commercial) 0C to +70C (Commercial)
安裝類型 Surface Mount Surface Mount
Configuration Technology EEPROM (non-volatile) —
In-System Programmability Yes (JTAG ISP) —
Number of Terminals 240 —
Package Code FQFP / RQFP —
Terminal Form Gull Wing —
Package Shape Square —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
MSL 等級 [DATA_NEEDED: MSL level] —
Series — MAX 9000
Family — MAX 9000 (third-generation Multiple Array MatriX)
Logic Array Blocks (LABs) — 35
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)

資料表與資源

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