EPM9560RC240-15C vs EPM9560RC240-15YY 比較
詳細並排比較 EPM9560RC240-15C 由 Intel 與 EPM9560RC240-15YY 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC240-15C | EPM9560RC240-15YY |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000A |
| Device Type | EEPROM-based CPLD | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks | 20 | — |
| User I/O Pins | 187 | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | — |
| 供應電壓 | 5.0 V | — |
| Operating Voltage Range | 3.3 V or 5 V | — |
| 封裝 | 240-pin RQFP (PowerQuad II) | — |
| Terminal Pitch | 0.5 mm | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| Process Technology | CMOS | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Logic Type | — | CMOS EEPROM-based CPLD |
| Number of Macrocells | — | 560 |
| Number of User I/O | — | 191 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 (JTAG) |
| Package Type | — | RQFP-240 (Plastic Quad Flat Pack) |
| Speed Grade | — | -15 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count for EPM9560] |