EPM9560RC240-15C vs EPM9560RC240-15YY Comparison
Detailed side-by-side comparison of EPM9560RC240-15C by Intel and EPM9560RC240-15YY by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC240-15C | EPM9560RC240-15YY |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000A |
| Device Type | EEPROM-based CPLD | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks | 20 | — |
| User I/O Pins | 187 | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage | 5.0 V | — |
| Operating Voltage Range | 3.3 V or 5 V | — |
| Package | 240-pin RQFP (PowerQuad II) | — |
| Terminal Pitch | 0.5 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) | 0 C to +70 C (commercial) |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| Process Technology | CMOS | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Logic Type | — | CMOS EEPROM-based CPLD |
| Number of Macrocells | — | 560 |
| Number of User I/O | — | 191 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 (JTAG) |
| Package Type | — | RQFP-240 (Plastic Quad Flat Pack) |
| Speed Grade | — | -15 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count for EPM9560] |