EPM9560RC240-15YY vs EPM9560RC240-15N 比較

詳細並排比較 EPM9560RC240-15YY 由 Intel 與 EPM9560RC240-15N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM9560RC240-15YY EPM9560RC240-15N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND NRND
Family MAX 9000A MAX 9000 (third-generation Multiple Array MatriX)
Logic Type CMOS EEPROM-based CPLD —
Number of Macrocells 560 —
Usable Gates 12,000 12,000
Number of User I/O 191 —
Maximum Operating Frequency 117.6 MHz —
Propagation Delay (tpd) 15 ns —
Supply Voltage (VCC) 5.0 V —
Programmability In-system via IEEE 1149.1 (JTAG) In-system programmable (IEEE 1532/JTAG)
Package Type RQFP-240 (Plastic Quad Flat Pack) —
安裝類型 Surface Mount Surface Mount
工作溫度 0 C to +70 C (commercial) 0C to +70C (Commercial)
Speed Grade -15 —
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count for EPM9560] 35
RoHS 狀態 Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Series — MAX 9000
Macrocells — 560
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
供應電壓 — 5.0 V
Logic Family — CMOS (EEPROM-based)
Boundary-Scan Test — JTAG (IEEE 1149.1)
封裝 — RQFP-240 (240-pin Plastic Quad Flat Pack)

資料表與資源

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