EPM9560RC304-15N vs EPM9560RC304-10 比較
詳細並排比較 EPM9560RC304-15N 由 Altera 與 EPM9560RC304-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC304-15N | EPM9560RC304-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | — |
| Usable Gates | 12,000 | 16000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 (estimated from 560 macrocells) | — |
| Maximum Operating Frequency (fMAX) | 117.6 MHz | — |
| Pin-to-Pin Propagation Delay | 15 ns (-15 speed grade) | 12 ns |
| Supply Voltage (VCCINT) | 5 V | — |
| 封裝 | RQFP-304 | RQFP-304 (RC) |
| User I/O Count | 304 (package-level) | — |
| Process Technology | High-performance CMOS EEPROM | 0.65 µm CMOS EEPROM |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Operating Temperature Grade | Commercial (suffix N) | — |
| RoHS 狀態 | Compliant (lead-free per suffix N marking) | ROHS3 Compliant |
| Device Type | — | CPLD / EPLD |
| Logic Elements | — | 560 |
| 腳位數 | — | 304 |
| Speed Grade | — | -10 |
| 供應電壓 | — | 5 V |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |
| User I/O Pins | — | 304 (package-limited) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Method | — | JTAG in-system (ISP) |
| 安裝類型 | — | Surface Mount |
| MSL 等級 | — | 3 (168 Hours) |