EPM9560RI208-10N vs EPM9560RI208-20 比較
詳細並排比較 EPM9560RI208-10N 由 Altera 與 EPM9560RI208-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RI208-10N | EPM9560RI208-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - third generation |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | 560 |
| Register Bits | 12,160 | — |
| User I/Os | 212 | — |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | — |
| Maximum Frequency | 100 MHz to 125 MHz | — |
| 供應電壓 | 5 V | — |
| 封裝 | 208-pin RQFP (PQFP) | 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm |
| 工作溫度 | -40C to +85C (Industrial grade, "RI" suffix) | [DATA_NEEDED: operating temperature range grade] |
| Programming Method | In-system via IEEE 1149.1 (JTAG) | — |
| MSL 等級 | 3 (168 Hours) | — |
| RoHS 狀態 | ROHS3 Compliant (per fpgalink) | [DATA_NEEDED: RoHS compliance status] |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| 安裝類型 | — | Surface Mount |