EPM9560RI208-10N vs EPM9560RI208-20 Comparison
Detailed side-by-side comparison of EPM9560RI208-10N by Altera and EPM9560RI208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-10N | EPM9560RI208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - third generation |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | 560 |
| Register Bits | 12,160 | — |
| User I/Os | 212 | — |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | — |
| Maximum Frequency | 100 MHz to 125 MHz | — |
| Supply Voltage | 5 V | — |
| Package | 208-pin RQFP (PQFP) | 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm |
| Operating Temperature | -40C to +85C (Industrial grade, "RI" suffix) | [DATA_NEEDED: operating temperature range grade] |
| Programming Method | In-system via IEEE 1149.1 (JTAG) | — |
| MSL Level | 3 (168 Hours) | — |
| RoHS Status | ROHS3 Compliant (per fpgalink) | [DATA_NEEDED: RoHS compliance status] |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| Mounting Type | — | Surface Mount |