EPM9560RI304 vs EPM9560RC304-15C 比較
詳細並排比較 EPM9560RI304 由 Altera 與 EPM9560RC304-15C 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C Obsolete規格比較
| 參數 | EPM9560RI304 | EPM9560RC304-15C |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 | — |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Maximum User I/O Pins | 216 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (IEEE 1149.1 JTAG) |
| JTAG Interface | IEEE Std. 1149.1 (JTAG) | — |
| 封裝 | 304-pin BFQFP/RQFP (HFQFP) | 304-pin RQFP |
| Package Code | HFQFP, square | — |
| Terminal Form | Gull wing | — |
| Number of Terminals | 304 | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks and Programmable Interconnect Array | Multiple Array MatriX (MAX), 3rd generation |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 560 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins (maximum) | — | 212 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| 供應電壓 | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| Program/Erase Endurance | — | 100 cycles minimum |
| 工作溫度 | — | 0 C to +70 C (Commercial) |