EPM9560WC208 vs EPM9560WC208-15 比較
詳細並排比較 EPM9560WC208 由 Altera 與 EPM9560WC208-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560WC208 | EPM9560WC208-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE Programmable Logic Device (CPLD) | EE PLD (Electrically Erasable Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| Flip-Flops | 772 | 772 |
| Maximum User I/O | 149 | — |
| 最大時脈頻率 | 117.6 MHz | 117.6 MHz |
| Propagation Delay (tpd, -15 grade) | 16.6 ns | — |
| 供應電壓 | 3.3 V or 5 V | — |
| Process Technology | CMOS, electrically erasable | — |
| 封裝 | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | 0.50 mm |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG | JTAG (IEEE 1149.1 boundary scan) |
| Configuration Memory | Non-volatile EE (instant-on) | — |
| Hot Socketing Support | Yes | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | RoHS3 Compliant (per third-party listings) |
| Technology | — | CMOS |
| User I/O Pins (max) | — | 149 |
| Propagation Delay (tPD) | — | 16.6 ns |
| Speed Grade | — | -15 |
| Supply Voltage - I/O | — | 3.3 V or 5.0 V (configurable) |