H5ANAG6NBJR-RDC vs H5ANAG6NBJR-UHC 比較
詳細並排比較 H5ANAG6NBJR-RDC 由 SK hynix 與 H5ANAG6NBJR-UHC 由 SK hynix. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | H5ANAG6NBJR-RDC | H5ANAG6NBJR-UHC |
|---|---|---|
| 品牌 | SK hynix | SK hynix |
| 類別 | DRAM | DRAM |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 記憶體類型 | DDR4 SDRAM | DDR4 SDRAM |
| Memory Organization | 16Gb x16 | — |
| Density | 16 Gb | 4 Gb |
| 資料速率 | 2666 Mbps (speed grade -RDC) | — |
| Supply Voltage (VDD) | 1.2 V | — |
| 介面 | Synchronous, double data rate | DDR4 (CMOS) |
| Clocking | Fully synchronous to both clock edges | — |
| 封裝 | FBGA (Ball Grid Array), surface mount | PBGA96 / FBGA-96 (TFBGA) |
| 安裝類型 | Surface Mount | — |
| Technology | CMOS | — |
| Standard | JEDEC DDR4 SDRAM | — |
| Application | Main memory | — |
| 工作溫度 | [DATA_NEEDED: Operating Temperature Range] | -40C to +95C |
| On-Die Termination (ODT) | Supported (DDR4 feature) | — |
| Bank Group Architecture | DDR4 bank groups (per JEDEC DDR4) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS Status] | RoHS Compliant |
| 組織 | — | 256M x 16 |
| Package Dimensions | — | 13 mm length (per JESD-30 R-PBGA-B96) |
| Access Mode | — | Multi Bank, Page Burst |
| Refresh | — | Auto / Self Refresh |
| Data Mask | — | Supported (DM function) |
| Asynchronous Reset | — | Supported |
| On-Chip Termination | — | Dynamic ODT |
| ZQ Calibration | — | Supported |
| Write Leveling | — | Supported |
| CRC | — | Supported |
| Supply Voltage Class | — | DDR4 (1.2 V class) |
| REACH Compliance | — | Compliant |
| ECCN | — | EAR99 |
| HTS Code | — | 8542.32.00.36 |
| CAS 延遲 | — | [DATA_NEEDED: CAS Latency] |
| Max Data Rate | — | [DATA_NEEDED: Max Data Rate] |