H5ANAG6NBJR-UHC vs H5AN4G6NBJR-PBC 比較
詳細並排比較 H5ANAG6NBJR-UHC 由 SK hynix 與 H5AN4G6NBJR-PBC 由 SK hynix. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | H5ANAG6NBJR-UHC | H5AN4G6NBJR-PBC |
|---|---|---|
| 品牌 | SK hynix | SK hynix |
| 類別 | DRAM | Memory ICs |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 記憶體類型 | DDR4 SDRAM | DDR4 SDRAM |
| Density | 4 Gb | — |
| 組織 | 256M x 16 | 256M x 16 (268435456 words x 16 bits) |
| 介面 | DDR4 (CMOS) | DDR4 (double data rate, synchronous) |
| 封裝 | PBGA96 / FBGA-96 (TFBGA) | FBGA-96 (PBGA96), rectangular |
| Package Dimensions | 13 mm length (per JESD-30 R-PBGA-B96) | — |
| Access Mode | Multi Bank, Page Burst | — |
| 工作溫度 | -40C to +95C | [DATA_NEEDED: temperature range for -C grade] |
| Refresh | Auto / Self Refresh | — |
| Data Mask | Supported (DM function) | — |
| Asynchronous Reset | Supported | — |
| On-Chip Termination | Dynamic ODT | — |
| ZQ Calibration | Supported | — |
| Write Leveling | Supported | — |
| CRC | Supported | — |
| Supply Voltage Class | DDR4 (1.2 V class) | — |
| RoHS 狀態 | RoHS Compliant | — |
| REACH Compliance | Compliant | — |
| ECCN | EAR99 | — |
| HTS Code | 8542.32.00.36 | — |
| CAS 延遲 | [DATA_NEEDED: CAS Latency] | [DATA_NEEDED: CAS latency for PBC speed grade] |
| Max Data Rate | [DATA_NEEDED: Max Data Rate] | — |
| Memory Density | — | 4 Gbit |
| Supply Voltage (VDD) | — | 1.2 V |
| Package Code | — | TFBGA |
| Number of Terminals | — | 96 |
| 安裝類型 | — | Surface Mount |
| 功能特色 | — | Auto self-refresh, data mask, asynchronous reset, dynamic ODT, ZQ calibration, write leveling, CRC |
| Data Rate / Speed Grade | — | [DATA_NEEDED: speed grade PBC data rate] |
| Process | — | CMOS |
| Lead-Free / Halogen-Free | — | Yes (per family datasheet, Lead-Free & Halogen-Free) |
| Temperature Grade | — | OTHER (per distributor listing) |