LS1021AXE7MQB vs LS1021AXE7KQB 比較
詳細並排比較 LS1021AXE7MQB 由 NXP Semiconductors 與 LS1021AXE7KQB 由 NXP Semiconductors. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
NXP Semiconductors
LS1021AXE7MQB - Layerscape 32-bit ARM SoC, 1.2GHz Dual-Core | NXP
LS1021AXE7MQB ✓ 啟用中規格比較
| 參數 | LS1021AXE7MQB | LS1021AXE7KQB |
|---|---|---|
| 品牌 | NXP Semiconductors | NXP Semiconductors |
| 類別 | Microcontrollers | Microcontrollers |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | QorIQ LS1 (Layerscape) | — |
| Core Architecture | ARM Cortex-A7, dual-core, 32-bit | — |
| Maximum Core Frequency | 1.2 GHz | — |
| 工作溫度 | -40C to +105C (industrial) | — |
| 封裝 | 525-FCPBGA, 19x19 mm | 525-FCPBGA (19 mm x 19 mm) |
| 安裝類型 | Surface Mount | — |
| Memory Controller | DDR3 / DDR4 with ECC (per datasheet) | — |
| Ethernet | 2x virtual TSEC (vTSEC) 10G-capable | — |
| PCIe | 2x PCIe Gen2 controllers | — |
| USB | USB 3.0 | — |
| SATA | SATA 3.0 | — |
| Display | LCDC (LCD controller) | — |
| CAN | Yes (CAN interfaces) | — |
| Security Engine | SEC (trusted boot, hardware crypto) | — |
| QUICC Engine | uQE (legacy TDM/HDLC support) | — |
| Silicon Revision | Rev 2.0 (per distributor description) | — |
| L2 Cache | [DATA_NEEDED: L2 cache size] | — |
| RoHS 狀態 | Compliant (per distributor) | — |
| Product Type | — | QorIQ communications processor |
| Processor Core | — | ARM Cortex-A7 |
| Core Count | — | 2 cores |
| Instruction Width | — | 32-bit |
| Maximum Listed Frequency | — | 1.0 GHz |
| Architecture | — | Layerscape |
| Product Tier | — | Value-performance tier |
| Package Pin or Ball Count | — | 525 balls |
| 工作溫度範圍 | — | -40°C to +105°C |
| ECC Protection | — | Supported by dual ARM Cortex-A7 cores |
| Virtualization Support | — | Supported |
| Security | — | Security enabled |
| Power Class | — | Sub-3 W processor |
| Performance | — | Over 7,000 CoreMarks |
| Target Application | — | Fanless, small-form-factor enterprise networking |
| 生命週期狀態 | — | Active |
| MSL 等級 | — | 3 (168 hours) |
| REACH Status | — | REACH unaffected |