LTC2150CUJ-14 vs LTC2155CUP-14 比較
詳細並排比較 LTC2150CUJ-14 由 Analog Devices 與 LTC2155CUP-14 由 Analog Devices. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Analog Devices
LTC2150CUJ-14 - 14-Bit 170Msps 1.8V ADC DDR LVDS | Analog Devices
LTC2150CUJ-14 ✓ 啟用中
規格比較
| 參數 | LTC2150CUJ-14 | LTC2155CUP-14 |
|---|---|---|
| 品牌 | Analog Devices | Analog Devices |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 解析度 | 14 bit | 14 bit |
| Number of Channels | 1 | 2 (dual, simultaneous sampling) |
| Sample Rate | 170 Msps | — |
| Architecture | Pipelined | Pipelined |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) | 1.7 V to 1.9 V (1.8 V nominal) |
| INL (typical) | ±0.85 LSB | — |
| DNL (typical) | ±0.25 LSB | — |
| Transition Noise | 1.82 LSBRMS | — |
| Missing Codes | None over temperature | — |
| Full-Power Sample/Hold Bandwidth | 1.25 GHz | — |
| Digital Output Interface | DDR LVDS | — |
| Encode Clock Inputs | Differential ENC+/ENC- (sine, PECL, LVDS, TTL, CMOS) | — |
| Clock Duty-Cycle Stabilizer | Optional (selectable) | — |
| Configuration Interface | Serial SPI port | — |
| Latency | 5 clock cycles | — |
| Power-Saving Modes | Sleep and Nap modes | — |
| 封裝 | 40-QFN (6 mm × 6 mm) with exposed pad | 64-QFN (9x9 mm) with exposed pad |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Compliant (Pb-free #PBF suffix) | Compliant (PBF suffix indicates Pb-free) |
| 取樣率 | — | 170 MSPS per channel |
| Input Type | — | Differential |
| 輸出類型 | — | Parallel CMOS / DDR LVDS selectable |
| Analog Input Bandwidth | — | 1.4 GHz |
| SNR | — | 70.1 dB (at 100 MHz input, per family datasheet) |
| SFDR | — | 88 dB (per family datasheet) |
| Power Consumption | — | [DATA_NEEDED: total power per pair at 170 Msps] |
| 工作溫度範圍 | — | 0C to +70C (C suffix = commercial) |
| MSL 等級 | — | [DATA_NEEDED] |