P5010NXN1QMB557 vs P5010NSN1QMB 比較
詳細並排比較 P5010NXN1QMB557 由 NXP Semiconductors 與 P5010NSN1QMB 由 NXP Semiconductors. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
NXP Semiconductors
P5010NXN1QMB557 - QorIQ P5 2GHz 64-Bit MPU | NXP 1295-FCPBGA
P5010NXN1QMB557 ✓ 啟用中NXP Semiconductors
P5010NSN1QMB - QorIQ P5010 SoC, 64-bit Power Arch, 2.0GHz, 1295-FCBGA | NXP
P5010NSN1QMB ✓ 啟用中規格比較
| 參數 | P5010NXN1QMB557 | P5010NSN1QMB |
|---|---|---|
| 品牌 | NXP Semiconductors | NXP Semiconductors |
| 類別 | Microcontrollers | Microcontrollers |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Manufacturer | NXP Semiconductors (formerly Freescale) | — |
| Series | QorIQ P5 | — |
| Core Architecture | PowerPC e5500, 64-bit | — |
| Number of Cores | 1 | — |
| Maximum Core Frequency | 2.0 GHz | 2.0 GHz |
| External Data Bus Width | 64-bit | — |
| Address Bus Width | 16-bit (per Microchip USA listing) | — |
| 封裝 | 1295-ball FCPBGA (37.5 x 37.5 mm) | 1295-FCBGA (37.5 x 37.5 mm) |
| Ball Pitch | 1.00 mm | — |
| JESD-30 Package Code | S-PBGA-B1295 | — |
| Process Technology | CMOS | — |
| Integrated Cache | Yes (L1 + L2) | — |
| Low-Power Mode Support | Yes | — |
| RoHS 狀態 | Compliant | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +105C |
| 安裝類型 | Surface Mount (BGA) | — |
| Architecture | — | Power Architecture e5500 (64-bit) |
| Core Count | — | 1 core |
| Cache (L1 Instruction per core) | — | 32 KB |
| Cache (L1 Data per core) | — | 32 KB |
| Cache (L2 shared frontside) | — | 1 MB |
| Memory Controller | — | DDR3 with ECC support |
| PCIe | — | PCI Express Gen 2 controllers integrated |
| Ethernet | — | Dual Gigabit Ethernet |
| High-Speed Interconnect | — | Serial RapidIO (SRIO) |
| Hardware Acceleration | — | DPAA (Data Path Acceleration Architecture) engine |
| Security Engine | — | SEC crypto engine integrated |
| Encryption | — | Hardware-accelerated |