RTAX2000SL-CGS624E vs RTAX2000S-1CGS624EV 比較
詳細並排比較 RTAX2000SL-CGS624E 由 Microchip Technology 與 RTAX2000S-1CGS624EV 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
RTAX2000SL-CGS624E - 2M-Gate Rad-Tolerant FPGA CGA-624 | Microchip
RTAX2000SL-CGS624E ✓ 啟用中Microchip Technology
RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624EV ✓ 啟用中規格比較
| 參數 | RTAX2000SL-CGS624E | RTAX2000S-1CGS624EV |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Logic Elements / CLBs | 21504 CLBs | — |
| Equivalent System Gates | 2000000 gates | — |
| Additional ASIC Gates | 250000 gates | — |
| Family | RTAX-S/SL Radiation-Tolerant FPGAs | — |
| Technology | CMOS, anti-fuse OTP | — |
| Radiation Tolerance | Radiation-tolerant (space-flight grade) | — |
| 封裝 | CBGA624 / CGA-624 ceramic column grid array | 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration | Live at power-up, one-time programmable | One-time programmable anti-fuse, live at power-up, single chip |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Arithmetic Support | Carry logic | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| 供應電壓 | [DATA_NEEDED: core supply voltage] | — |
| Maximum I/O | [DATA_NEEDED: maximum user I/O count for CG624 package] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Qualification | [DATA_NEEDED: QML qualification level] | — |
| System Gates | — | 2,000,000 |
| Logic Cells (CLBs) | — | 21504 |
| Total Cells | — | 32256 |
| Additional ASIC Equivalent Gates | — | 250000 |
| Core Supply Voltage | — | 1.5 V nominal (1.425 V to 1.575 V) |
| Process Technology | — | 0.15 um CMOS |
| Maximum Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| SEU Immunity | — | SEU-hardened registers, immune to single-event upsets to specified LET threshold |
| SEU Rate | — | < 10-10 errors/bit-day |
| Product Family | — | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs |
| Thermal Resistance Basis | — | JEDEC JESD51 simulation conditions (per datasheet) |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |
| Maximum User I/O | — | [DATA_NEEDED: user I/O count] |