STM32G051K8T6 vs STM32G051K6T6 比較
詳細並排比較 STM32G051K8T6 由 STMicroelectronics 與 STM32G051K6T6 由 STMicroelectronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
STMicroelectronics
STM32G051K6T6 - 64MHz Cortex-M0+ 32KB MCU | STMicroelectronics
STM32G051K6T6 ✓ 啟用中規格比較
| 參數 | STM32G051K8T6 | STM32G051K6T6 |
|---|---|---|
| 品牌 | STMicroelectronics | STMicroelectronics |
| 類別 | Microcontrollers | Microcontrollers |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Product Type | 32-bit ARM Cortex-M0+ microcontroller | 32-bit Arm Cortex-M0+ microcontroller |
| Series | STM32G0 mainstream series | — |
| CPU Core | Arm 32-bit Cortex-M0+ | — |
| Maximum CPU Frequency | 64 MHz | 64 MHz |
| Flash Memory | 64 KB | 32 KB (32K x 8) |
| Flash Organization | 64K x 8 | — |
| SRAM | 18 KB | 18 KB |
| SRAM Parity Support | 16 KB with hardware parity check | — |
| 工作電源電壓 | 1.7 V to 3.6 V | — |
| USART Count | 2 | 2 |
| ADC | Integrated | — |
| DAC | Integrated | — |
| Timer Resources | Integrated timers | — |
| Communication Interfaces | Integrated communication interfaces | — |
| 封裝 | 32-LQFP, 7 x 7 mm | 32-pin LQFP (7x7 mm) |
| 安裝類型 | Surface mount | Surface mount |
| 工作溫度 | -40 °C to +85 °C / +105 °C / +125 °C across device variants | — |
| Flash Protection | Protected and securable area | [DATA_NEEDED: detailed flash protection and securable-area configuration] |
| RoHS 狀態 | unknown | unknown |
| REACH Status | unknown | unknown |
| AEC-Q100 Qualification | unknown | not_applicable |
| Manufacturer | — | STMicroelectronics |
| Core Architecture | — | Arm Cortex-M0+ 32-bit RISC |
| Operating Voltage Range | — | 1.7 V to 3.6 V |
| Timer Support | — | General-purpose timers |
| Operating Temperature Options | — | -40°C to 85°C, -40°C to 105°C, or -40°C to 125°C depending on the device variant |
| Exact Temperature Grade of STM32G051K6T6 | — | [DATA_NEEDED: exact temperature grade for the T6 order code] |
| Digital Core Supply | — | VCORE, internally generated by an embedded linear voltage regulator |
| VREF+ Connection | — | Internally connected to VDD on packages without a VREF+ pin |
| Internal Reference Buffer Requirement | — | Must remain disabled when VREF+ is internally connected to VDD |