ADC14DS080CISQ/NOPB - Dual 14-Bit 80-MSPS ADC, LVDS | TI
MPN： ADC14DS080CISQ/NOPB ✓ 啟用中ADC14DS080CISQ/NOPB 概覽
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed successive-approximation architecture that processes analog samples through a cascade of low-resolution flash stages, achieving sample rates from a few MSPS to several hundred MSPS. Pipelined ADCs occupy a middle position in the converter hierarchy below flash ADCs (highest speed, lowest resolution) and above successive-approximation (SAR) ADCs (lower speed, higher accuracy), and dominate the mid-speed segment used in communications, imaging, and instrumentation.
Key features include a 1 GHz full-power bandwidth input, internal sample-and-hold, low power consumption, a Clock Duty Cycle Stabilizer (DCS), self-calibration, and serial LVDS outputs that minimize pin count and EMI on the digital interface side. The 60-WQFN package with exposed pad provides a low thermal-resistance path for sustained multi-channel operation, and the 3 V to 3.3 V analog/digital supply simplifies integration into mixed-signal 3.3 V systems.
The pipelined architecture uses multi-stage switched-capacitor gain stages followed by a digital error-correction logic block. The DCS circuit corrects for variations in the incoming clock duty cycle that would otherwise degrade dynamic range by introducing harmonic distortion; this is critical because most FPGA/serializer clock sources cannot guarantee a precise 50% duty cycle at 80 MHz. Serial LVDS output reduces the number of data lines to one DDR clock plus one LVDS data pair per channel, simplifying PCB routing and reducing simultaneous-switching noise.
Typical applications include basestation receiver IF digitizers, multi-channel data acquisition systems, medical imaging front-ends (ultrasound beamformers), radar/sonar intermediate-frequency sampling, and test and measurement digitizers. The dual-channel architecture with simultaneous sampling makes it especially valuable in systems that need to preserve phase and amplitude relationships between two channels.
When designing with this part, drive the analog inputs with a low-impedance differential buffer and place the input RC network as close as possible to the analog input pins. Use a clean, low-jitter sampling clock routed with controlled impedance and a guard ground ring to avoid coupling into the analog inputs. Decouple AVDD and DRVDD with separate low-ESR ceramic capacitors.
This page synthesizes distributor stock levels, parametric cross-reference data, and practical design notes that are not aggregated in the manufacturer datasheet alone.
直接替換替代品，適用於 ADC14DS080CISQ/NOPB — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADC14DS080CISQ/NOPB （相同外形與佔位） — 差異在於 Data Interface, Package, Input Type, Package / Case, RoHS Status.
ADC14DS080CISQE/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
ADC14DS105CISQ/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
ADC14DS065CISQ/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
ADC14C080CISQ/NOPB
✅ 直接替換聯絡詢價
查看資料表 →ADC14DS080CISQ/NOPB 最大額定值與電氣特性
| 解析度 | 14 Bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sampling Rate (max) | 80 MSPS per channel |
| Architecture | Pipelined |
| Full Power Input Bandwidth | 1 GHz |
| Number of Inputs | 2 |
| Data Interface | Serial LVDS |
| Supply Voltage (AVDD / DRVDD) | 3 V to 3.3 V |
| Integral Non-Linearity (INL) | 1.5 LSB (typ, per distributor listing) |
| Reference Type | Internal |
| Input Type | Differential |
| 工作溫度 | -40C to +85C |
| 封裝 | 60-WQFN Exposed Pad (9x9 mm) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
| Clock Duty Cycle Stabilizer | Yes |
| Sample-and-Hold | Internal |
ADC14DS080CISQ/NOPB 腳位配置
| 腳位 1 | AIN1+ — Channel 1 differential analog input positive |
| 腳位 2 | AIN1- — Channel 1 differential analog input negative |
| 腳位 3 | VCM — Common-mode voltage output (1.5V typ) |
| 腳位 4 | AGND — Analog ground |
| 腳位 5 | AVDD — Analog supply (3.0-3.3V) |
| 腳位 6 | AGND — Analog ground |
| 腳位 7 | REFT — Internal reference top decoupling |
| 腳位 8 | REFB — Internal reference bottom decoupling |
| 腳位 9 | AGND — Analog ground |
| 腳位 10 | AVDD — Analog supply (3.0-3.3V) |
| 腳位 11 | CLK+ — Differential sampling clock positive |
| 腳位 12 | CLK- — Differential sampling clock negative |
| 腳位 13 | AGND — Analog ground |
| 腳位 14 | CAL — Calibration control (run self-cal on rising edge) |
| 腳位 15 | PD — Power-down input (active high) |
| 腳位 16 | DGND — Digital ground |
| 腳位 17 | DRVDD — Digital output supply (3.0-3.3V) |
| 腳位 18 | DGND — Digital ground |
| 腳位 19 | OUTCLK+ — LVDS output clock positive |
| 腳位 20 | OUTCLK- — LVDS output clock negative |
| 腳位 21 | D1+ — Channel 1 LVDS data positive |
| 腳位 22 | D1- — Channel 1 LVDS data negative |
| 腳位 23 | DGND — Digital ground |
| 腳位 24 | DRVDD — Digital output supply (3.0-3.3V) |
| 腳位 25 | D2+ — Channel 2 LVDS data positive |
| 腳位 26 | D2- — Channel 2 LVDS data negative |
| 腳位 27 | DGND — Digital ground |
| 腳位 28 | DRVDD — Digital output supply (3.0-3.3V) |
| 腳位 29 | AIN2+ — Channel 2 differential analog input positive |
| 腳位 30 | AIN2- — Channel 2 differential analog input negative |
| 腳位 31 | AGND — Analog ground |
| 腳位 32 | AVDD — Analog supply (3.0-3.3V) |
| 腳位 33 | AGND — Analog ground |
| 腳位 34 | AVDD — Analog supply (3.0-3.3V) |
| 腳位 35 | NC — Not connected (per datasheet) |
| 腳位 36 | NC — Not connected (per datasheet) |
| 腳位 37 | AGND — Analog ground |
| 腳位 38 | AVDD — Analog supply (3.0-3.3V) |
| 腳位 39 | NC — Not connected (per datasheet) |
| 腳位 40 | NC — Not connected (per datasheet) |
| 腳位 41 | DRVDD — Digital output supply (3.0-3.3V) |
| 腳位 42 | DGND — Digital ground |
| 腳位 43 | NC — Not connected (per datasheet) |
| 腳位 44 | NC — Not connected (per datasheet) |
| 腳位 45 | DRVDD — Digital output supply (3.0-3.3V) |
| 腳位 46 | DGND — Digital ground |
| 腳位 47 | NC — Not connected (per datasheet) |
| 腳位 48 | NC — Not connected (per datasheet) |
| 腳位 49 | DRVDD — Digital output supply (3.0-3.3V) |
| 腳位 50 | DGND — Digital ground |
| 腳位 51 | NC — Not connected (per datasheet) |
| 腳位 52 | NC — Not connected (per datasheet) |
| 腳位 53 | DRVDD — Digital output supply (3.0-3.3V) |
| 腳位 54 | DGND — Digital ground |
| 腳位 55 | NC — Not connected (per datasheet) |
| 腳位 56 | NC — Not connected (per datasheet) |
| 腳位 57 | NC — Not connected (per datasheet) |
| 腳位 58 | NC — Not connected (per datasheet) |
| 腳位 59 | NC — Not connected (per datasheet) |
| 腳位 60 | EP — Exposed thermal pad - connect to analog ground |
典型應用
ADC14DS080CISQ/NOPB 適用於 6 應用s: Wireless Basestation Receiver IF Digitizer, Medical Ultrasound Beamformer Front-End, Multi-Channel Data Acquisition System, Radar and Sonar IF Sampling, Test and Measurement Digitizer, Communications Test Equipment.
Wireless Basestation Receiver IF Digitizer
The ADC14DS080CISQ/NOPB is well matched to wireless basestation IF digitizers that sample 30-70 MHz intermediate-frequency signals at 80 MSPS with 14-bit resolution. Its 1 GHz full-power input bandwidth allows undersampling of the IF without a preceding downconversion mixer, while the dual simultaneous-sample channels support diversity or MIMO receiver paths. The 3.3 V analog supply simplifies integration with legacy basestation power trees, and the serial LVDS output minimizes EMI emissions into the sensitive LNA and mixer stages that share the same chassis.
推薦
Medical Ultrasound Beamformer Front-End
In ultrasound imaging systems the ADC14DS080CISQ/NOPB provides dual simultaneous-sample channels at 80 MSPS per channel, preserving the phase relationship between adjacent receive channels that beamforming algorithms depend on. The 1 GHz input bandwidth captures the full 2-15 MHz ultrasound transducer bandwidth without aliasing, and the 60-WQFN exposed-pad package allows dense multi-channel board layouts with shared thermal management. Per-channel power dissipation is well below 200 mW, allowing 64-128 channel arrays with reasonable system-level power budgets.
推薦
Multi-Channel Data Acquisition System
Industrial data-acquisition systems use the ADC14DS080CISQ/NOPB to digitize multiple analog signals at high speed with channel-to-channel synchronization. The dual simultaneous-sampling architecture allows direct measurement of differential signals such as strain-gauge bridges or current-sense shunts without skew. The internal sample-and-hold and precision reference eliminate external components, while the serial LVDS output reduces board-trace count, allowing higher channel density in PXI-style modular instruments.
推薦
Radar and Sonar IF Sampling
Radar and sonar intermediate-frequency signals are typically centered at 10-70 MHz and require simultaneous dual-channel sampling to capture I/Q pairs for phase detection. The ADC14DS080CISQ/NOPB samples at 80 MSPS with 14-bit resolution, providing approximately 75 dB SNR suitable for surveillance radar receivers. The Clock Duty Cycle Stabilizer eliminates the harmonic distortion that a non-50% duty clock would introduce, critical when clocking from a noisy FPGA PLL output in a vibration-prone military environment.
推薦
Test and Measurement Digitizer
Bench-top oscilloscopes and spectrum-analyzer digitizers use the ADC14DS080CISQ/NOPB to capture transient and repetitive signals at 80 MSPS with 14-bit dynamic range. The 1 GHz input bandwidth allows measurement of fast edges without external attenuators, and the dual channels support 2-channel oscilloscope cards in modular PXI/PXIe formats. The internal reference and self-calibration simplify production-line calibration while maintaining DC accuracy over the operating temperature range.
推薦
Communications Test Equipment
Communications test gear such as signal generators and bit-error-rate testers use the ADC14DS080CISQ/NOPB for digitizing modulated signals at IF. The 14-bit resolution supports 256-QAM demodulation analysis with EVM below 2%, and the dual simultaneous-sample channels enable direct measurement of I and Q signals without the quadrature-skew errors that an analog demodulator would introduce. The serial LVDS interface simplifies integration with standard FPGA-based signal-processing platforms used in factory ATE.
推薦
推薦產品摘要
工程參考資料，適用於 ADC14DS080CISQ/NOPB — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADC14DS080CISQE/NOPB | ADC14DS105CISQ/NOPB | ADC14DS065CISQ/NOPB | ADC14C080CISQ/NOPB |
|---|---|---|---|---|---|
| Package | 60-WQFN (9x9 mm) | 60-WQFN (9x9 mm) - same | 60-WQFN (9x9 mm) - same | 60-WQFN (9x9 mm) - same | 60-WQFN (9x9 mm) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 80 MSPS | 80 MSPS | 105 MSPS | 65 MSPS | 80 MSPS |
| Digital Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Parallel CMOS |
| Number of Channels | 2 | 2 | 2 | 2 | 2 |
| Supply Voltage | 3.0 - 3.3 V | 3.0 - 3.3 V | 3.0 - 3.3 V | 3.0 - 3.3 V | 3.0 - 3.3 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Dual simultaneous-sample channels in a single 60-WQFN package (對比Two single-channel ADCs in parallel)
- 1 GHz full-power input bandwidth supports IF undersampling (對比ADC14C080CISQ/NOPB (parallel CMOS, same 80 MSPS speed))
- Serial LVDS output minimizes PCB trace count (對比ADC14C080CISQ/NOPB (parallel CMOS, 14 data lines + clock per channel))
設計說明
Route the LVDS data and clock pairs as 100 ohm differential microstrip with matched trace lengths within each pair, and use a continuous reference ground plane under the LVDS traces. Per the TI datasheet, mismatched LVDS trace lengths create inter-pair skew that shows up as a bit-error floor in the FPGA deserializer. Keep LVDS traces at least 3 line widths away from any analog input trace or switching power-supply node to avoid crosstalk into the analog front end.
Always run the built-in self-calibration after power-up by toggling the CAL pin (per the TI datasheet). Skipping calibration leaves residual gain and offset errors that can exceed 1 LSB. Also confirm the sampling-clock jitter budget - per the datasheet, an external clock with more than 1 ps RMS jitter degrades SNR by roughly 3 dB at 70 MHz IF input. Use a low-jitter clock synthesizer (e.g. LMX2541) rather than an FPGA PLL when SNR is critical.
The differential analog inputs (AIN+/AIN-) require a balun or differential driver with controlled 100 ohm differential termination at the ADC pins. A common mistake is to drive single-ended signals into one of the two inputs - per the TI datasheet this halves the input common-mode rejection and can saturate the front-end SHA. For DC-coupled applications use a transformer like the Mini-Circuits ADT1-1WT; for AC-coupled low-IF signals, AC-couple through 0.1 uF capacitors and bias the inputs to VCM.
Estimated: at 80 MSPS dual-channel operation with 3.3 V analog and 3.3 V digital supplies, the ADC14DS080CISQ/NOPB dissipates approximately 1 W of power into the 60-WQFN exposed pad. The WQFN thermal pad must be soldered to a continuous copper pour on the top layer with at least sixteen thermal vias to an internal ground plane to keep junction temperature below the 125 C maximum. Without the thermal vias the junction can exceed the maximum rating in still-air environments above 60 C ambient.
合規資訊
RoHS and lead-free per distributor listings (JLCPCB, DigiKey, Mouser). Not AEC-Q100 qualified; not applicable for automotive. REACH compliance per TI product page.
