ADC14C080CISQ/NOPB - 14-Bit 80-MSPS ADC, 32-WQFN | Texas Instruments
MPN: ADC14C080CISQ/NOPB ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $23.5 | $23.50 |
| 10 | $21.15 | $211.50 |
| 100 | $18.8 | $1,880.00 |
| 500 | $16.95 | $8,475.00 |
| 1,000 | $15.2 | $15,200.00 |
ADC14C080CISQ/NOPB Overview
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog voltage and quantizes each sample into a fixed-width binary code word. Pipelined ADCs like the ADC14C080 use multiple low-resolution flash stages operating in parallel to achieve high sample rates while keeping power and die area modest, making them the workhorse architecture for communications baseband, IF sampling, medical imaging, and bench-top instrumentation. In the broader system taxonomy, ADCs sit under data converters, which in turn belong to the mixed-signal / data acquisition IC family within power management and signal chain semiconductors.
Key headline parameters include 14-bit resolution, 80 MSPS maximum sample rate, 1.0 GHz full-power input bandwidth, an aperture jitter typically specified in the sub-picosecond range, and an SNR of approximately 71 dBFS at the Nyquist input. The device features a duty-cycle stabilizer to maintain dynamic performance over a wide range of input clock duty cycles, an internal or external reference option, and CMOS-compatible parallel digital outputs. Programmable gain and offset calibration are accessible via the SPI-compatible serial control interface, and the part includes power-down modes for portable operation.
The architecture combines an input track-and-hold with eight pipelined 1.5-bit stages followed by a final 3-bit flash, with on-chip digital error correction. This produces 14-bit linear output with low integral and differential nonlinearity and excellent spurious-free dynamic range (SFDR) above 80 dBc at low input frequencies. The internal reference can be overdriven by an external source for multi-channel gain matching across ADCs.
Typical applications include cellular base-station IF sampling, cable-modem downstream capture, medical ultrasound beamforming front-ends, portable and handheld oscilloscopes, radar and lidar intermediate-frequency digitizers, and CCD/camera imaging pipelines. The wide input bandwidth also makes the ADC14C080 useful as a general-purpose digitizer on the bench or in factory-test racks. In IF sampling applications the high bandwidth lets designers place the ADC directly after a 200 MHz IF stage without a preceding down-conversion mixer.
When designing with this part, pay attention to analog input drive impedance, clock jitter (the 14-bit/80-MSPS target translates to a jitter budget on the order of hundreds of femtoseconds), and the layout of the WQFN exposed pad - it must be soldered to a continuous ground copper pour for thermal dissipation and low-impedance return paths. Decoupling the 2.5V AVDD and 3.3V DRVDD pins with 0.1 µF plus 10 µF ceramic capacitors placed within 5 mm of each pin is essential to meet published SNR and SFDR numbers.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet.
Drop-in alternatives for ADC14C080CISQ/NOPB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC14C080CISQ/NOPB (same form factor and footprint) — differing in Package, Input Type, Data Interface, RoHS Status, Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC14C080CISQE/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
ADC14C080CISQ
✅ Drop-In📋 Reference alternative (not in catalog)
ADC14C080CISQE
✅ Drop-In📋 Reference alternative (not in catalog)
ADC14C080CISQ/NOPB Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 1 |
| Sample Rate (Max) | 80 MSPS |
| Architecture | Pipelined |
| Input Bandwidth | 1.0 GHz |
| Analog Supply Voltage | 2.5 V (nominal) |
| Digital I/O Supply Voltage | 3.3 V (nominal) |
| Data Interface | Parallel (CMOS) |
| Input Type | Single-ended / Differential |
| Package | 32-WQFN (5x5 mm) with exposed pad |
| Operating Temperature | -40 C to +85 C |
| Mounting Type | Surface Mount |
| MSL Level | 2 |
| RoHS Status | Compliant (per TI datasheet) |
| Lead-Free Finish | Yes (NOPB suffix) |
ADC14C080CISQ/NOPB Pin Configuration
| Pin 1 | AVDD — Analog supply voltage (2.5 V nominal) |
| Pin 2 | VIN+ — Differential analog input, positive |
| Pin 3 | VIN- — Differential analog input, negative |
| Pin 4 | VCM — Common-mode voltage output |
| Pin 5 | AGND — Analog ground |
| Pin 6 | REFT — Top reference decoupling |
| Pin 7 | REFB — Bottom reference decoupling |
| Pin 8 | REFIN — External reference input |
| Pin 9 | REFOUT — Internal reference output |
| Pin 10 | AGND — Analog ground |
| Pin 11 | AVDD — Analog supply voltage |
| Pin 12 | PD — Power-down control input |
| Pin 13 | DCS — Duty-cycle stabilizer enable |
| Pin 14 | OE — Output enable (active low) |
| Pin 15 | CLK+ — Differential clock input, positive |
| Pin 16 | CLK- — Differential clock input, negative |
| Pin 17 | DRVDD — Digital output supply (3.3 V) |
| Pin 18 | DRGND — Digital ground |
| Pin 19 | D13 — Parallel data output, MSB |
| Pin 20 | D12 — Parallel data output |
| Pin 21 | D11 — Parallel data output |
| Pin 22 | D10 — Parallel data output |
| Pin 23 | D9 — Parallel data output |
| Pin 24 | D8 — Parallel data output |
| Pin 25 | D7 — Parallel data output |
| Pin 26 | D6 — Parallel data output |
| Pin 27 | D5 — Parallel data output |
| Pin 28 | D4 — Parallel data output |
| Pin 29 | D3 — Parallel data output |
| Pin 30 | D2 — Parallel data output |
| Pin 31 | D1 — Parallel data output |
| Pin 32 | D0 — Parallel data output, LSB |
Typical Applications
ADC14C080CISQ/NOPB is suitable for 6 applications: Cellular Base Station IF Sampling, Medical Ultrasound Beamforming Front-End, Portable Oscilloscope and DSO Front-End, Radar and Lidar IF Digitiser, CCD / CMOS Camera Imaging Pipeline, Cable Modem and Broadband Receiver.
Cellular Base Station IF Sampling
The ADC14C080CISQ/NOPB is widely used in cellular base-station receiver chains for intermediate-frequency (IF) signal digitisation. Its 1.0 GHz full-power input bandwidth allows direct sampling of IF signals in the 70-250 MHz range without an analogue down-conversion mixer, simplifying the receiver BOM. The 14-bit resolution and ~71 dBFS SNR provide sufficient dynamic range for WCDMA, LTE, and 5G NR carrier capture when used with a low-noise AGC stage ahead of the ADC. The 80 MSPS sample rate comfortably meets carrier bandwidth requirements while keeping clock-tree design straightforward on a standard FPGA. Place the ADC adjacent to the FPGA with matched-length parallel output traces to preserve timing margin.
Recommended
Medical Ultrasound Beamforming Front-End
In medical ultrasound systems, the ADC14C080CISQ/NOPB serves as the per-channel digitiser immediately following the time-gain-compensation (TGC) and low-noise amplifier stage. The 14-bit dynamic range comfortably covers the typical 60-70 dB ultrasound receive signal range after TGC, while the 80 MSPS sample rate aligns with industry-standard probe centre frequencies of 2-10 MHz sampled at IF. The CMOS parallel output bus interfaces directly to FPGA-based digital beamformer pipelines that perform delay-and-sum focusing across receive channels. The exposed-pad 32-WQFN package supports the dense channel-per-board layouts required in cart-based and portable ultrasound systems.
Recommended
Portable Oscilloscope and DSO Front-End
Handheld and bench-top digital-storage oscilloscopes (DSOs) targeting the 50-200 MHz bandwidth class commonly use the ADC14C080CISQ/NOPB as the per-channel digitiser after the analogue attenuator and trigger path. The 1.0 GHz input bandwidth supports the 200 MHz -3 dB bandwidth target with margin, while the 80 MSPS sample rate delivers 40 MHz of alias-protected capture bandwidth per channel. Designers value the duty-cycle stabilizer because it relaxes clock-driver specifications in cost-sensitive oscilloscope architectures. The low-power 65 MSPS mode further extends battery runtime on portable oscilloscope platforms.
Recommended
Radar and Lidar IF Digitiser
Automotive and industrial radar front-ends, plus lidar receivers, use the ADC14C080CISQ/NOPB to digitise the IF output of the mixer that down-converts the reflected RF signal to baseband or low-IF. The 1.0 GHz input bandwidth allows IF sampling architectures at 100-300 MHz IF frequencies, eliminating a second mixing stage and reducing BOM cost. The 14-bit resolution gives adequate spur and clutter rejection for short-range radar (SRR) and industrial distance-measurement lidar channels. The 32-WQFN footprint and exposed-pad thermal path suit the rugged -40 C to +85 C industrial environment required for vehicle-mounted and factory-floor radar modules.
Recommended
CCD / CMOS Camera Imaging Pipeline
Scientific and industrial CCD/CMOS camera designs use the ADC14C080CISQ/NOPB to digitise the analogue output of image sensors after correlated double sampling. The 14-bit resolution captures the full dynamic range of high-end scientific CMOS sensors, while the 80 MSPS sample rate supports standard 4K and high-speed line-scan sensor pixel rates. The CMOS parallel output integrates directly with FPGA image-pipeline IP cores that perform demosaicing, colour correction, and compression. The exposed-pad package provides the thermal headroom required for the dense multi-ADC layouts common in line-scan machine-vision cameras.
Recommended
Cable Modem and Broadband Receiver
Downstream cable modem and DOCSIS receiver paths use the ADC14C080CISQ/NOPB to digitise the IF output of the tuner block. The 1.0 GHz input bandwidth comfortably handles the 1 GHz downstream cable spectrum when used in an undersampling architecture, eliminating an analogue down-conversion stage. The 14-bit resolution provides the carrier-to-noise ratio required for 256-QAM and 4096-QAM downstream constellations. The CMOS parallel output bus feeds directly into DOCSIS MAC-layer FPGAs, and the device's wide operating temperature range suits outdoor cable-modem termination equipment (CMTS) headend hardware.
Recommended
Recommended Products Summary
Engineering reference data for ADC14C080CISQ/NOPB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC14C080CISQE/NOPB | ADC14C080CISQ | ADC14C080CISQE |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-WQFN (5x5) | 32-WQFN (5x5) - same | 32-WQFN (5x5) - same | 32-WQFN (5x5) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate (Max) | 80 MSPS | 80 MSPS | 80 MSPS | 80 MSPS |
| Input Bandwidth | 1.0 GHz | 1.0 GHz | 1.0 GHz | 1.0 GHz |
| Analog Supply | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Lead-Free (NOPB) | Yes | Yes | No (leaded) | No (leaded) |
| Reel Quantity | 1000 | 250 | 1000 | 250 |
Key Differentiators
- Wide 1.0 GHz input bandwidth supports direct IF undersampling (vs ADC14C080CISQ (leaded))
- Lower minimum order quantity option available (vs ADC14C080CISQE/NOPB)
- Drop-in compatibility with all same-family variants (vs ADC14C080CISQE (leaded))
Design Notes
Decouple each AVDD and DRVDD pin with a 0.1 µF X7R ceramic capacitor placed within 5 mm of the pin, plus a bulk 10 µF ceramic on each supply rail. The 2.5 V AVDD and 3.3 V DRVDD rails should originate from low-noise LDO regulators (such as the TI TPS7A4700) rather than switching converters to preserve the ADC's SNR floor. Estimated noise: a 100 mV ripple on AVDD would degrade SNR by approximately 6 dB at the 14-bit level; keep ripple below 5 mVpp.
The exposed thermal pad (EP) of the 32-WQFN package MUST be soldered to a continuous ground copper pour that extends at least 8 mm in all directions beneath and around the part. Star-ground the analog and digital grounds at a single point near the ADC's AGND/DRGND pins to prevent digital switching noise from coupling into the analog front-end. Match the length of all 14 parallel data output traces (D0-D13) to within 1 mm to preserve the parallel-bus timing margin at 80 MSPS.
Driven clock jitter above 1 ps RMS will noticeably degrade SNR at 80 MSPS - the theoretical SNR jitter limit at 70 MHz IF is approximately SNR_jitter = 20·log10(1 / (2π·fIN·tj)). Use a low-jitter clock driver (such as the TI CDCM7005) rather than an FPGA-generated LVCMOS clock for the CLK+/CLK- differential inputs. Engage the internal duty-cycle stabilizer (DCS) when the incoming clock duty cycle deviates more than 5% from 50%, otherwise harmonic distortion will rise.
Compliance Information
Lead-free (NOPB) finish per TI part numbering convention; RoHS/REACH compliance inferred from NOPB suffix and TI product page. AEC-Q100 qualification not applicable - this is an industrial/consumer-grade part, not automotive grade.
