ADS6223IRGZR - Dual 12-bit 80MSPS ADC, Serial LVDS | TI
MPN： ADS6223IRGZR ✓ 啟用中ADS6223IRGZR 概覽
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them into discrete digital codes. Pipeline ADCs such as the ADS6223 family use a multi-stage switched-capacitor architecture to achieve sample rates from tens to hundreds of MSPS while maintaining low power consumption. ADCs sit in the signal chain hierarchy between analog front ends (amplifiers, filters) and digital processing blocks (FPGAs, DSPs, ASICs), and are essential in data acquisition, communications, and imaging systems where analog signals must be digitized for analysis or storage.
The ADS6223IRGZR offers 12-bit resolution, programmable output data rates of 65/80/105/125 MSPS, a coarse gain of 3.5 dB and a programmable fine gain of up to 6 dB, and a serial LVDS output interface for low-noise board-level data transfer. Internally, two simultaneously-sampling track-and-hold stages feed a shared pipelined core that delivers deterministic latency suitable for I/Q demodulation. The device is specified over the industrial -40C to +85C temperature range and operates from a single 3.3 V analog and digital supply.
Typical applications include medical imaging ultrasound front ends, multichannel industrial data acquisition cards, communications receiver I/Q baseband digitization, and handheld test and measurement instruments. The LVDS serial interface reduces board trace count compared to parallel CMOS ADCs, enabling dense multi-channel layouts on standard FR-4.
When designing with this device, provide low-impedance decoupling on each supply pin and a quiet analog ground plane to achieve the rated SNR. The exposed thermal pad must be soldered to the PCB ground for both thermal dissipation and electrical reference; failing to solder the EP will degrade linearity and may cause device failure.
This page consolidates distributor pricing, drop-in alternatives, and practical design notes not present on the manufacturer product page or in the standalone datasheet.
直接替換替代品，適用於 ADS6223IRGZR — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS6223IRGZR （相同外形與佔位） — 差異在於 Analog Supply Voltage, Package, Operating Temperature Range, Resolution, Input Type.
ADS6223IRGZT
✅ 直接替換📋 參考替代品（不在目錄中）
ADS6224IRGZR
✅ 直接替換聯絡詢價
查看資料表 →ADS6225IRGZR
✅ 直接替換聯絡詢價
查看資料表 →ADS6222IRGZT
✅ 直接替換📋 參考替代品（不在目錄中）
ADS6129IRGZ25
✅ 直接替換聯絡詢價
查看資料表 →ADS61B29IRGZ25
✅ 直接替換聯絡詢價
查看資料表 →ADS6223IRGZR 最大額定值與電氣特性
| Manufacturer | Texas Instruments |
| Part Number | ADS6223IRGZR |
| Description | Dual-Channel, 12-Bit, 65/80/105/125 MSPS ADC with Serial LVDS Interface |
| 解析度 | 12 bit |
| Number of Channels | 2 |
| Sample Rate (Max) | 125 MSPS |
| Sample Rate (This Variant) | 80 MSPS |
| Architecture | Pipelined |
| Data Interface | Serial LVDS (1-Wire / 2-Wire) |
| Analog Supply Voltage | 3.3 V (typical) |
| Digital Supply Voltage | 3.3 V (typical) |
| Input Type | Differential |
| Coarse Gain | 3.5 dB |
| Programmable Fine Gain | 0 to 6 dB |
| Simultaneous Sampling | Yes (two sample-and-hold stages) |
| 工作溫度 | -40C to +85C |
| 封裝 / 外殼 | 48-VFQFN Exposed Pad (RGZ) |
| 安裝類型 | Surface Mount |
| No. of Terminals | 48 |
| Terminal Form | No Lead |
| Package Code | HVQCCN |
| RoHS 狀態 | Compliant |
| Lead Free | Yes |
| 生命週期狀態 | Active |
ADS6223IRGZR 腳位配置
| 腳位 1 | AVDD — Analog 3.3 V supply |
| 腳位 2 | AVSS — Analog ground |
| 腳位 3 | INA+ — Channel A differential analog input (positive) |
| 腳位 4 | INA- — Channel A differential analog input (negative) |
| 腳位 5 | VCM — Common-mode voltage output (reference for inputs) |
| 腳位 6 | INB+ — Channel B differential analog input (positive) |
| 腳位 7 | INB- — Channel B differential analog input (negative) |
| 腳位 8 | AVSS — Analog ground |
| 腳位 9 | AVDD — Analog 3.3 V supply |
| 腳位 10 | AVSS — Analog ground |
| 腳位 11 | CLKDIV — Clock divider control |
| 腳位 12 | RESET — Hardware reset (active low) |
| 腳位 13 | SCLK — Serial interface clock |
| 腳位 14 | SDATA — Serial interface data |
| 腳位 15 | SEN — Serial interface enable (active low) |
| 腳位 16 | DGND — Digital ground |
| 腳位 17 | DVDD — Digital 3.3 V supply |
| 腳位 18 | DGND — Digital ground |
| 腳位 19 | LVDS_DAT_P — Channel A LVDS data positive |
| 腳位 20 | LVDS_DAT_N — Channel A LVDS data negative |
| 腳位 21 | LVDS_CLK_P — LVDS clock positive |
| 腳位 22 | LVDS_CLK_N — LVDS clock negative |
| 腳位 23 | DVDD — Digital 3.3 V supply |
| 腳位 24 | DGND — Digital ground |
| 腳位 25 | LVDS_DA_P — Channel A LVDS data positive (frame) |
| 腳位 26 | LVDS_DA_N — Channel A LVDS data negative (frame) |
| 腳位 27 | LVDS_DB_P — Channel B LVDS data positive (frame) |
| 腳位 28 | LVDS_DB_N — Channel B LVDS data negative (frame) |
| 腳位 29 | DGND — Digital ground |
| 腳位 30 | DVDD — Digital 3.3 V supply |
| 腳位 31 | DGND — Digital ground |
| 腳位 32 | NC — Not connected (per datasheet) |
| 腳位 33 | NC — Not connected (per datasheet) |
| 腳位 34 | NC — Not connected (per datasheet) |
| 腳位 35 | AVSS — Analog ground |
| 腳位 36 | AVDD — Analog 3.3 V supply |
| 腳位 37 | AVSS — Analog ground |
| 腳位 38 | NC — Not connected (per datasheet) |
| 腳位 39 | NC — Not connected (per datasheet) |
| 腳位 40 | NC — Not connected (per datasheet) |
| 腳位 41 | AVSS — Analog ground |
| 腳位 42 | AVDD — Analog 3.3 V supply |
| 腳位 43 | AVSS — Analog ground |
| 腳位 44 | AVDD — Analog 3.3 V supply |
| 腳位 45 | AVSS — Analog ground |
| 腳位 46 | AVDD — Analog 3.3 V supply |
| 腳位 47 | AVSS — Analog ground |
| 腳位 48 | AVDD — Analog 3.3 V supply |
典型應用
ADS6223IRGZR 適用於 6 應用s: Medical Ultrasound Imaging Front End, Multichannel Industrial Data Acquisition, Communications Receiver I/Q Baseband Digitization, Handheld Test and Measurement Instruments, Radar and Lidar Signal Processing, Software Defined Radio (SDR) Platforms.
Medical Ultrasound Imaging Front End
The ADS6223IRGZR's dual simultaneously-sampling 12-bit channels and 80 MSPS sample rate make it an ideal candidate for medical ultrasound receiver beamformer front ends, where each channel of an N-element transducer array must be digitized at high speed. Placed immediately after the TGC (time-gain-compensated) LNA, the ADC's 3.5 dB coarse gain plus programmable 0-6 dB fine gain aligns the input full-scale to the ultrasound echo dynamic range without an external PGA, reducing bill-of-materials and improving noise figure. The serial LVDS interface reduces board traces versus parallel CMOS, simplifying dense multi-channel PCB layouts inside the ultrasound probe handle. Per TI's datasheet, the differential inputs reject common-mode pickup from piezo transducer cables, improving image SNR in clinical imaging systems where a 1 dB dynamic-range improvement translates to better lesion detection.
推薦
Multichannel Industrial Data Acquisition
In industrial data acquisition cards and modular I/O systems, the ADS6223IRGZR provides two simultaneous 12-bit conversions per device at 80 MSPS, enabling 8 or 16 channel boards to be built by stacking multiple ADCs with shared clocking. The differential inputs reject common-mode noise from motor drives and power-conversion stages common on factory floors, while the 3.3 V single-supply operation simplifies power-tree design alongside 3.3 V FPGAs. The serial LVDS interface allows the ADCs to be located near the signal sources with minimal trace count, reducing crosstalk in dense backplanes. Per TI's datasheet typical performance, the ADC maintains 12-bit no-missing-codes operation across the industrial -40C to +85C range, which is critical for process-control equipment operating in uncontrolled factory environments.
推薦
Communications Receiver I/Q Baseband Digitization
The ADS6223IRGZR is well-matched to communications receiver I/Q baseband digitization, where the two simultaneously-sampling channels can capture the I and Q outputs of a quadrature demodulator at up to 80 MSPS. This provides approximately 35 MHz of usable analog input bandwidth per channel (well within Nyquist for narrowband and moderate-bandwidth receivers), with the ADC's deterministic pipeline latency simplifying digital I/Q correction and channelization in the downstream FPGA. Per TI's datasheet, the LVDS serial interface minimizes EMI and ground-bounce issues versus wide parallel CMOS buses, which is particularly valuable in densely-populated receiver cards. The 12-bit resolution delivers approximately 70 dB SNR, which is sufficient for many narrowband commercial and amateur-radio receiver designs targeting IF frequencies up to 70 MHz.
推薦
Handheld Test and Measurement Instruments
Handheld oscilloscopes, spectrum analyzers, and portable test instruments benefit from the ADS6223IRGZR's combination of dual channels, 80 MSPS sample rate, and low 3.3 V supply current. Two channels per IC allow a 2- or 4-channel scope to be built with fewer ADCs than competing single-channel parts, reducing both PCB area and power consumption - critical for battery-powered handheld tools. Per TI's datasheet, the serial LVDS interface reduces connector pin count between the analog front-end board and the digital processing board, enabling smaller, more reliable instrument enclosures. Industrial temperature grade ensures the ADC operates reliably across outdoor and laboratory temperature conditions without derating, while the exposed-pad VQFN package provides adequate thermal performance in sealed enclosures without active cooling.
推薦
Radar and Lidar Signal Processing
Radar and lidar receiver chains require fast, low-noise dual-channel digitization of intermediate-frequency or baseband signals, which is a direct fit for the ADS6223IRGZR's dual 12-bit 80 MSPS architecture. Placed after the IF mixer or transimpedance amplifier, the ADC's differential inputs reject common-mode noise from RF switching power supplies in the radar chassis, and the simultaneous sampling preserves phase information critical for beamforming and Doppler processing. Per TI's datasheet, the LVDS interface minimizes EMI emissions from the digital side, important for sensitive receiver systems where any spurious coupling can desensitize the front-end. The ADC's low latency and deterministic pipeline characteristic simplify the digital signal processing required for SAR (synthetic aperture radar) image formation and lidar point-cloud extraction.
推薦
Software Defined Radio (SDR) Platforms
Software-defined radio platforms rely on fast, dual-channel ADCs placed close to the antenna or IF stage to digitize wideband RF signals for digital demodulation. The ADS6223IRGZR's dual 12-bit channels at 80 MSPS support bandwidths up to approximately 35 MHz per channel, which is suitable for narrowband amateur, commercial, and experimental SDR applications including FM, DAB, DVB, and experimental wideband FM. Per TI's datasheet, the LVDS interface allows the ADC to be placed on an RF daughtercard with minimal digital noise coupling back into the analog front-end, and the 3.3 V operation simplifies integration with common SDR FPGA platforms. The exposed-pad VQFN package is compatible with standard reflow profiles used in SDR kit manufacturing.
推薦
推薦產品摘要
工程參考資料，適用於 ADS6223IRGZR — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS6223IRGZT | ADS6224IRGZR | ADS6225IRGZR | ADS6222IRGZT |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-48 (RGZ) Exposed Pad | VQFN-48 (RGZ) - same | VQFN-48 (RGZ) - same | VQFN-48 (RGZ) - same | VQFN-48 (RGZ) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sample Rate (Max) | 80 MSPS | 80 MSPS | 105 MSPS | 125 MSPS | 65 MSPS |
| Number of Channels | 2 (simultaneous sampling) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Data Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Dual simultaneous-sampling channels in a single VQFN-48 IC (對比ADS6223IRGZT)
- Family-up compatible with 105/125 MSPS speed grades (對比ADS6225IRGZR)
- Industry-standard serial LVDS output reduces board trace count (對比ADS62P45IRGCR)
設計說明
Place 0.1 uF ceramic decoupling capacitors as close as possible to each AVDD and DVDD supply pin, and add a 10 uF bulk capacitor near the package. Per TI's datasheet recommendations, keep analog and digital supply traces separated with their own decoupling networks, and stitch the analog and digital ground planes together at a single point under the exposed pad. The exposed thermal pad (EP) MUST be soldered to the PCB ground plane to ensure thermal dissipation and electrical reference - failing to solder the EP will degrade linearity.
Route the differential analog inputs (INA+/INA-, INB+/INB-) as matched-length 100 ohm differential pairs to preserve common-mode rejection and reduce second-order distortion. Keep the LVDS output traces short (under 5 cm where possible) and route them away from analog input traces; the LVDS interface's high-speed edges can couple into the analog inputs and degrade SNR. Use a continuous ground plane beneath the analog input traces to maintain a controlled 100 ohm differential impedance per the JEDEC/JEP150 reference design pattern.
Common pitfalls when designing with the ADS6223IRGZR: (1) Not soldering the exposed thermal pad - causes linearity drift and possible device failure; (2) Using a single shared ground plane under both analog and digital sections - causes digital noise to couple into the analog inputs; (3) Driving single-ended inputs without the VCM reference - the differential inputs require a common-mode bias near VCM to operate linearly; (4) Exceeding the maximum sample rate of the chosen speed grade - the ADS6223 is rated for 80 MSPS, but the family also includes 105 MSPS (ADS6224) and 125 MSPS (ADS6225) variants; check the speed grade marking before PCB bring-up.
For optimum SNR, drive the ADS6223IRGZR analog inputs with a fully-differential driver such as the THS4521 or LMH6624, AC-coupled with the VCM reference providing bias. Estimated: at 80 MSPS with a 10 MHz input, a properly-driven ADS6223 achieves approximately 70 dBFS SNR; missing the differential driver or terminating the inputs improperly can reduce SNR by 5-10 dB. Use a low-jitter clock source (LMK03806 or equivalent) - clock jitter above 1 ps RMS directly degrades SNR per the standard SNR_jitter = 20*log10(1/(2*pi*f_in*sigma_jitter)) formula.
合規資訊
RoHS and lead-free per TI product page; REACH compliance confirmed by TI documentation. Industrial temperature grade, not AEC-Q100 qualified (automotive variants would use a different MPN suffix). Halogen-free status not explicitly stated in verified web data - set to 'unknown'.
