ADS61B29IRGZ25 - 12-Bit 250MSPS Buffered ADC | Texas Instruments
MPN： ADS61B29IRGZ25 ✗ 停產ADS61B29IRGZ25 概覽
An ADC (Analog-to-Digital Converter) is a data-conversion IC that samples continuous-time analog signals and outputs discrete digital codes. The 12-bit resolution class sits in a hierarchy between 8/10-bit general-purpose converters and 14/16-bit precision converters, balancing dynamic range against conversion speed. The ADS61B29 belongs to the pipelined ADC family, which uses multiple low-resolution stages to achieve high sample rates (>100 MSPS) at moderate resolution - ideal for communications, radar, and test-and-measurement front ends where wide capture bandwidth matters more than absolute DC precision.
Key features include 250 MSPS maximum sample rate, integrated high-impedance analog input buffer, LVDS parallel data interface, single 3.3V analog supply, internal sample-and-hold ratio of 1:1, and industrial operating temperature range of -40C to +85C. The pipelined architecture delivers consistent dynamic performance across the full Nyquist bandwidth, with low spurious and harmonic distortion suitable for multi-carrier receiver designs.
The ADS61B29 uses a switched-capacitor pipeline core with proprietary calibration to maintain linearity, while the front-end analog buffer provides a high-impedance differential input that tolerates a wide variety of source impedances. Differential LVDS outputs minimize switching noise on the digital supply rail, allowing the part to coexist with sensitive analog circuitry on shared 3.3V planes when proper decoupling is observed.
Typical applications include multi-carrier GSM/EDGE base-station receivers, cable-headend digitizers, radar and SAR signal acquisition, test-and-measurement digitizer cards, and medical imaging front-ends. The integrated buffer and 250 MSPS throughput also suit software-defined radio (SDR) platforms that need wide instantaneous bandwidth at a moderate resolution.
When designing with this device, drive the analog inputs differentially (typically through a balun or active differential amplifier) to achieve the datasheet's SFDR and SNR numbers at high input frequencies; the integrated buffer reduces but does not eliminate the sensitivity to common-mode noise at the analog inputs.
直接替換替代品，適用於 ADS61B29IRGZ25 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS61B29IRGZ25 （相同外形與佔位） — 差異在於 Package, Resolution, Operating Temperature Range, Analog Supply Voltage, Output Interface.
ADS61B49IRGZ25
✅ 直接替換聯絡詢價
查看資料表 →ADS61B49IRGZR
✅ 直接替換📋 參考替代品（不在目錄中）
ADS61B29IRGZR
✅ 直接替換📋 參考替代品（不在目錄中）
ADS6129IRGZ25
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →ADS61B29IRGZ25 最大額定值與電氣特性
| 解析度 | 12 bits |
| Sample Rate (Maximum) | 250 MSPS |
| Number of Input Channels | 1 |
| Input Type | Differential |
| Input Architecture | Integrated High-Impedance Analog Buffer (Pipelined) |
| Data Interface | LVDS, Parallel |
| Configuration | S/H-ADC |
| Number of A/D Converters | 1 |
| S/H:ADC Ratio | 1:1 |
| Analog Supply Voltage | 3.3 V |
| Power Dissipation (Typical at 250 MSPS) | 790 mW |
| Architecture | Pipelined |
| 工作溫度範圍 | -40C to +85C |
| 封裝 | 48-VQFN (RGZ) 7x7 mm |
| 安裝類型 | Surface Mount |
| Temperature Grade | Industrial |
| Part Status (Digi-Key) | Discontinued at Digi-Key |
| Terminal Form | No Lead |
| Package Code | HVQCCN |
ADS61B29IRGZ25 腳位配置
| 腳位 1 | AVDD — Analog 3.3V supply |
| 腳位 2 | AGND — Analog ground |
| 腳位 3 | INP — Differential analog input (positive) |
| 腳位 4 | INN — Differential analog input (negative) |
| 腳位 5 | AGND — Analog ground |
| 腳位 6 | AVDD — Analog 3.3V supply |
| 腳位 7 | VCM — Common-mode voltage reference |
| 腳位 8 | AGND — Analog ground |
| 腳位 9 | RESET — Hardware reset, active low |
| 腳位 10 | SCLK — Serial interface clock |
| 腳位 11 | SDATA — Serial interface data |
| 腳位 12 | SEN — Serial interface enable |
| 腳位 13 | DRVDD — Digital LVDS driver supply |
| 腳位 14 | DRGND — Digital driver ground |
| 腳位 15 | DRVDD — Digital LVDS driver supply |
| 腳位 16 | DRGND — Digital driver ground |
| 腳位 17 | D0+ — LVDS data output bit 0 (positive) |
| 腳位 18 | D0- — LVDS data output bit 0 (negative) |
| 腳位 19 | D1+ — LVDS data output bit 1 (positive) |
| 腳位 20 | D1- — LVDS data output bit 1 (negative) |
| 腳位 21 | D2+ — LVDS data output bit 2 (positive) |
| 腳位 22 | D2- — LVDS data output bit 2 (negative) |
| 腳位 23 | D3+ — LVDS data output bit 3 (positive) |
| 腳位 24 | D3- — LVDS data output bit 3 (negative) |
| 腳位 25 | D4+ — LVDS data output bit 4 (positive) |
| 腳位 26 | D4- — LVDS data output bit 4 (negative) |
| 腳位 27 | D5+ — LVDS data output bit 5 (positive) |
| 腳位 28 | D5- — LVDS data output bit 5 (negative) |
| 腳位 29 | D6+ — LVDS data output bit 6 (positive) |
| 腳位 30 | D6- — LVDS data output bit 6 (negative) |
| 腳位 31 | D7+ — LVDS data output bit 7 (positive) |
| 腳位 32 | D7- — LVDS data output bit 7 (negative) |
| 腳位 33 | D8+ — LVDS data output bit 8 (positive) |
| 腳位 34 | D8- — LVDS data output bit 8 (negative) |
| 腳位 35 | D9+ — LVDS data output bit 9 (positive) |
| 腳位 36 | D9- — LVDS data output bit 9 (negative) |
| 腳位 37 | D10+ — LVDS data output bit 10 (positive) |
| 腳位 38 | D10- — LVDS data output bit 10 (negative) |
| 腳位 39 | D11+ — LVDS data output bit 11 (positive) |
| 腳位 40 | D11- — LVDS data output bit 11 (negative) |
| 腳位 41 | DRGND — Digital driver ground |
| 腳位 42 | DRVDD — Digital LVDS driver supply |
| 腳位 43 | CLKOUT+ — LVDS clock output (positive) |
| 腳位 44 | CLKOUT- — LVDS clock output (negative) |
| 腳位 45 | CLKP — Differential clock input (positive) |
| 腳位 46 | CLKN — Differential clock input (negative) |
| 腳位 47 | AGND — Analog ground |
| 腳位 48 | EP — Exposed thermal pad - connect to analog ground |
典型應用
ADS61B29IRGZ25 適用於 6 應用s: Multi-Carrier GSM/EDGE Base-Station IF Sampling, Cable Headend Downstream Digitizer, Radar and SAR Signal Acquisition, Test-and-Measurement Digitizer Cards, Software-Defined Radio (SDR) Platforms, Medical Imaging Front Ends.
Multi-Carrier GSM/EDGE Base-Station IF Sampling
The ADS61B29IRGZ25's integrated high-impedance analog input buffer makes it well-suited for multi-carrier GSM/EDGE base-station IF sampling receivers. At 250 MSPS and 12-bit resolution, the converter captures 125 MHz of instantaneous Nyquist bandwidth, enough for several adjacent IF carriers from a shared antenna chain. The buffer tolerates moderate source-impedance mismatch from the upstream SAW filter, simplifying the analog front end; the trade-off versus the unbuffered ADS6129 is roughly 200 mW higher dissipation. Pin-compatible 14-bit upgrade to ADS61B49IRGZ25 available on the same PCB footprint.
推薦
Cable Headend Downstream Digitizer
Cable-headend downstream digitizers benefit from the ADS61B29IRGZ25's 250 MSPS throughput and integrated analog input buffer, which can be driven directly from the cable modem downstream chain without an additional ADC driver. The 12-bit resolution captures QAM constellations of 256-QAM and below with adequate SNR margin; the integrated buffer reduces PCB complexity and BOM cost compared with a discrete driver/transformer front end. Designers transitioning to higher-order QAM can drop in the 14-bit ADS61B49IRGZ25 on the same 48-VQFN footprint without board rework.
推薦
Radar and SAR Signal Acquisition
Radar and synthetic-aperture radar (SAR) signal-acquisition boards use the ADS61B29IRGZ25 to digitize wide-bandwidth IF returns at up to 250 MSPS, with the integrated analog buffer simplifying the front end in space-constrained array electronics. The pipelined architecture delivers consistent SFDR across the Nyquist bandwidth, enabling high-fidelity capture of chirped-pulse returns. Industrial temperature grade (-40C to +85C) and the 48-VQFN with exposed thermal pad support rugged enclosures. The 14-bit ADS61B49IRGZ25 in the same package offers improved dynamic range for SAR with low-RCS targets.
推薦
Test-and-Measurement Digitizer Cards
Modular test-and-measurement digitizer cards - PXI, LXI, USB-based scopes - leverage the ADS61B29IRGZ25's 250 MSPS sample rate and high input impedance (via the integrated buffer) to handle mid-bandwidth signal capture without a custom front end. The 12-bit resolution matches the typical dynamic range of mid-tier digitizers, while the LVDS parallel interface streamlines data transfer to an FPGA on the same card. Pin-compatible upgrade to the 14-bit ADS61B49IRGZ25 increases vertical resolution without PCB rework, supporting platform families that span multiple resolution tiers.
推薦
Software-Defined Radio (SDR) Platforms
Wide-band software-defined radio (SDR) platforms use the ADS61B29IRGZ25 to digitize a 100+ MHz slice of RF spectrum at 12-bit resolution, with the integrated analog input buffer simplifying the interface to the LNA/mixer chain. At 250 MSPS the converter covers many popular ham, commercial, and surveillance bands without external filtering retuning between modes. The part's 790 mW power budget fits thermal envelopes typical of modular SDR enclosures when paired with the low-power ADS6129IRGZ25 option on the same footprint for power-sensitive deployments.
推薦
Medical Imaging Front Ends
Medical imaging front ends - including ultrasound beamformer IF stages, optical-coherence tomography receivers, and portable MRI receive chains - take advantage of the ADS61B29IRGZ25's 250 MSPS throughput and integrated analog buffer to digitize broadband signals with minimal board real estate. The 12-bit resolution is sufficient for envelope detection and beam-form subtraction; the industrial -40C to +85C operating range supports clinical and pre-hospital environments. Designers targeting improved dynamic range can move to the pin-compatible 14-bit ADS61B49IRGZ25 without redesigning the layout.
推薦
推薦產品摘要
工程參考資料，適用於 ADS61B29IRGZ25 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS61B49IRGZ25 | ADS61B49IRGZR | ADS61B29IRGZR | ADS6129IRGZ25 |
|---|---|---|---|---|---|
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same | 48-VQFN (RGZ) 7x7 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bits | 14 bits (+17%) | 14 bits | 12 bits (same) | 12 bits (same) |
| Sample Rate (Max) | 250 MSPS | 250 MSPS | 250 MSPS | 250 MSPS | 250 MSPS |
| Integrated Input Buffer | Yes | Yes | Yes | Yes | No (requires external ADC driver) |
| Power Dissipation (Typical at 250 MSPS) | 790 mW | ~790 mW (similar) | ~790 mW | 790 mW | ~590 mW (-25%) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Data Interface | LVDS Parallel | LVDS Parallel | LVDS Parallel | LVDS Parallel | LVDS Parallel |
| Lifecycle Status | Obsolete (Discontinued at Digi-Key) | Verify on TI product page | Verify on TI product page | Verify on TI product page | Verify on TI product page |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Integrated high-impedance analog input buffer (對比ADS6129)
- 12-bit resolution in same family as 14-bit ADS61B49 (對比ADS61B49IRGZ25)
- Pin-compatible across Z25 partial-reel and R full-reel packaging suffixes (對比ADS61B29IRGZR (R suffix))
設計說明
The ADS61B29IRGZ25 draws 790 mW typical at 250 MSPS from the 3.3 V analog supply, with a separate DRVDD rail for the LVDS output drivers. Decouple AVDD and DRVDD close to their respective pins with 0.1 uF X7R ceramics plus a 10 uF bulk cap, and route the analog and digital returns to a single-point ground under the exposed thermal pad (EP) to avoid coupling LVDS switching transients into the analog front end. Use independent ferrite-bead-isolated rails if AVDD and DRVDD are sourced from the same 3.3 V supply.
Drive the differential analog inputs (INP/INN) through a balun or differential amplifier matched to 100 ohm differential; the integrated analog input buffer tolerates moderate impedance mismatch but not severe imbalance. Per the TI datasheet, AC-coupling caps on INP/INN should be sized to present a low impedance at the highest input frequency (e.g., 0.1 uF X7R above 10 MHz IF). Keep the differential traces length-matched within 1 mm and route them over a continuous ground plane to preserve SFDR at high input frequencies.
Estimated: with 790 mW dissipation in the 48-VQFN (RGZ) 7x7 mm package and the exposed thermal pad soldered to the PCB, junction-to-ambient thermal resistance drops below 30 C/W on a 4-layer FR4 board with 4 square inches of unbroken inner ground plane. At 85C ambient, junction temperature stays well below the 125C limit. Do not run the part without soldering the EP to the ground plane - floating the pad raises theta_JA sharply and risks thermal shutdown.
Per the TI datasheet, place the clock-generation circuitry (a low-jitter PLL or clock buffer such as LMK04803) within 25 mm of the CLKP/CLKN pins to minimize jitter-induced SNR degradation at 250 MSPS. Series-terminate the LVDS output pairs (D0+ through D11+, CLKOUT+) with 100 ohm differential near the device, and route each LVDS pair length-matched and skew-controlled (<10 ps) to the receiving FPGA. Bypass the EP to a continuous analog ground pour on layer 2, not a stitched digital ground.
Do not apply a DC-coupled input without DC-biasing the INP/INN common-mode to the VCM voltage (typically 1.65 V) - the integrated buffer is not designed for input common-modes outside its linear range, and overdrive will distort SFDR. Do not exceed the AVDD maximum of 3.6 V or apply signals before AVDD/DRVDD have ramped up; the reset sequence should assert RESET before or simultaneously with supplies. Finally, do not assume the ADS61B29IRGZR/Z25 variant can be substituted for an unbuffered part - both share the same datasheet, but the buffer changes the analog front-end requirements.
合規資訊
RoHS compliance and lead-free terminal finish (No Lead) inferred from the verified distributor data showing a 48-VQFN (RGZ) package. REACH compliance follows TI's standard policy. Industrial temperature grade (-40C to +85C) is not AEC-Q100 qualified - choose a Q100-grade ADC for automotive designs. Halogen-free status not explicitly stated in the verified data; refer to TI environmental compliance documents.
