ADS62C17IRGCR - Dual 11-Bit 200MSPS ADC | Texas Instruments
MPN： ADS62C17IRGCR ✓ 啟用中ADS62C17IRGCR 概覽
An analog-to-digital converter (ADC) is a critical data-converter component that converts continuous analog signals into discrete digital values for digital signal processors and FPGAs. The ADS62C17 belongs to the high-speed pipelined ADC family, designed for sampling rates in the hundreds of mega-samples per second, and sits within the broader data-acquisition hierarchy used in communications, test and measurement, and radar systems.
Key features include dual 11-bit resolution with no missing codes, a maximum sampling rate of 200 MSPS, 90 dBc SFDR at Fin = 10 MHz, and 79.8 dBFS SNR at a 125 MHz input per TI data. The 64-VQFN package includes an exposed thermal pad for heat dissipation. The device operates from a 3.3V analog supply and 1.8V digital supply with typical power consumption of 1.1 W.
The ADS62C17 uses a pipelined architecture with digital error correction, achieving excellent linearity. SNRBoost digitally processes the output to improve SNR in a selected frequency band, particularly useful in multi-carrier receivers where weak signals must be extracted from strong interferers. It also includes an internal reference and a flexible clock input with duty-cycle stabilization.
Typical applications include multi-carrier GSM/UMTS/LTE base stations, software-defined radios, radar systems, and test and measurement equipment. The high sampling rate and dynamic performance suit direct IF sampling architectures, reducing system complexity and cost.
When designing with this ADC, pay careful attention to power supply decoupling and clock jitter, as both directly impact SNR and SFDR. The exposed pad must be soldered to a solid ground plane to ensure proper thermal and electrical performance. Pricing as of 2026-08-30 should be confirmed with distributors.
直接替換替代品，適用於 ADS62C17IRGCR — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS62C17IRGCR （相同外形與佔位） — 差異在於 Package.
ADS62C17IRGC25
✅ 直接替換聯絡詢價
查看資料表 →ADS62P29IRGCR
⚡ 相同封裝 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADS6422IRGCR
⚡ 相同封裝📋 參考替代品（不在目錄中）
ADS4246IRGCR
⚡ 相同封裝 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADS62C17IRGCR 最大額定值與電氣特性
| 解析度 | 11 bit |
| Number of Channels | 2 |
| 取樣率 | 200 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| SNR | 79.8 dBFS at 125 MHz input |
| SFDR | 90 dBc at Fin = 10 MHz |
| Output Interface | Parallel / Serial / LVDS |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V |
| Power Consumption | 1.1 W typical |
| Special Features | SNRBoost (TI proprietary) |
| Reference | Internal |
| Clock Features | Duty-cycle stabilization |
| 封裝 | 64-VQFN (RGC) 9x9 mm with exposed pad |
| 安裝類型 | Surface Mount |
ADS62C17IRGCR 64-vqfn (rgc) 9x9 mm with exposed pad 腳位配置指南
ADS62C17IRGCR（64-vqfn (rgc) 9x9 mm with exposed pad 封裝）的腳位配置。 此類比元件具有輸入、輸出與電源腳位。偏移歸零、補償與致能腳位配置請參閱製造商資料表。適用於訊號調理與放大器電路。
無詳細腳位定義資料： ADS62C17IRGCR.
請參閱 資料表 以查看完整腳位配置。
典型應用
ADS62C17IRGCR 適用於 6 應用s: Multi-Carrier Wireless Base Stations, Software-Defined Radio, Radar and Electronic Warfare Receivers, Test and Measurement Instrumentation, Medical Ultrasound Imaging, Industrial Instrumentation and DAQ.
Multi-Carrier Wireless Base Stations
The ADS62C17's dual 11-bit 200 MSPS sampling and 90 dBc SFDR at 10 MHz make it well-suited to multi-carrier GSM/UMTS/LTE base station receivers. Its TI SNRBoost technology improves in-band SNR where weak carriers sit next to strong interferers, directly raising uplink sensitivity. Sampling at 200 MSPS enables wideband direct-IF architectures that eliminate a mixer stage, reducing BOM cost and board area. With about 1.1 W total power in the compact 64-VQFN package, it fits dense multi-sector radio cards with constrained thermal budgets.
推薦
Software-Defined Radio
For SDR receivers, the ADS62C17 provides two synchronized 11-bit channels at 200 MSPS, supporting wide instantaneous bandwidth in direct-conversion and direct-IF topologies. The LVDS output interface transfers data to FPGAs with low pin count and low EMI, while duty-cycle stabilization relaxes clock constraints. SNRBoost lets the receiver dynamically enhance SNR in the channel of interest as waveforms change, a natural fit for reconfigurable SDR platforms covering multiple bands with a single RF-to-digital front end.
推薦
Radar and Electronic Warfare Receivers
Pulsed radar and EW receivers benefit from the ADS62C17's 200 MSPS dual sampling, which resolves short pulses and wide chirp bandwidths. The 79.8 dBFS SNR at a 125 MHz input preserves small-target returns, while 90 dBc SFDR prevents strong clutter from masking weak echoes. Dual-channel sampling supports I/Q demodulation in digital receivers. The 1.1 W power dissipation in the exposed-pad VQFN supports conduction-cooled defense boards where airflow is unavailable.
推薦
Test and Measurement Instrumentation
Digitizers and oscilloscope front ends use the ADS62C17's dual 200 MSPS channels to capture fast transients with 11-bit accuracy. Interleaving or simultaneous dual-channel capture enables time-correlated measurements. The parallel output mode simplifies interface design in instrument backplanes, while the internal reference reduces external component count. Designers should buffer the analog inputs with high-linearity drivers to preserve the converter's 90 dBc SFDR at 10 MHz input frequencies.
推薦
Medical Ultrasound Imaging
Ultrasound beamformers require many synchronized ADC channels; the dual-channel ADS62C17 halves package count versus single-channel converters, reducing board space in high-channel-count probes. The 200 MSPS rate supports high-resolution harmonic imaging, and 90 dBc SFDR preserves weak echo detail near strong transmit leakage. The 64-VQFN 9x9 mm footprint with exposed pad supports dense multilayer beamforming boards, while LVDS outputs keep channel-count wiring manageable across the card.
推薦
Industrial Instrumentation and DAQ
Wideband industrial data acquisition cards use the ADS62C17 to digitize vibration, acoustic emission, and RF monitoring signals with 200 MSPS per channel. The 3.3V/1.8V supply pair integrates easily with standard industrial rails via TI LDOs or PMICs. SNRBoost can be tuned to the monitoring band of interest, improving effective resolution without raising sample rate demands on the FPGA or DSP. The exposed-pad package must be soldered to a ground plane for reliable 1.1 W dissipation.
推薦
推薦產品摘要
工程參考資料，適用於 ADS62C17IRGCR — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS62C17IRGC25 | ADS62P29IRGCR | ADS6422IRGCR | AD9268BCPZ-125 |
|---|---|---|---|---|---|
| Package | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same package family | 64-VQFN (RGC) 9x9 mm - same package family | LQFP-64 - different package |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices |
| Resolution | 11 bit | 11 bit | 12 bit | 14 bit | 16 bit |
| Sampling Rate | 200 MSPS | 200 MSPS | 250 MSPS | 125 MSPS | 125 MSPS |
| Channels | 2 | 2 | 2 | 2 | 2 |
主要差異化特點
- SNRBoost in-band SNR enhancement (對比ADS6422IRGCR)
- Higher sample rate than 14-bit family peers (對比ADS6422IRGCR)
- True same-die drop-in configuration variant (對比ADS62C17IRGC25)
設計說明
Clock jitter directly limits SNR: for an 11-bit ADC sampling a 125 MHz input, total aperture jitter must be kept below roughly 1 ps rms to preserve full dynamic range. Use a dedicated low-noise PLL (e.g., LMX2572LP class) with a crystal reference, route the sample clock as a short differential pair with solid ground reference, and enable the ADS62C17's built-in duty-cycle stabilization to relax input clock duty-cycle requirements.
The ADS62C17 requires 3.3V analog and 1.8V digital supplies with about 1.1 W typical total power. Filter switching-regulator outputs with a low-noise LDO before the analog supply, since supply ripple degrades SFDR. Decouple each supply pin with 0.1uF ceramics placed within 2 mm of the pin, plus bulk 10uF capacitance. Separate analog and digital ground returns except at the exposed pad.
The 64-VQFN (RGC) exposed thermal pad is the primary thermal and ground path for 1.1 W dissipation. Solder it to a solid ground plane with an array of at least 25 via-in-pad connections (7x7 grid typical per TI datasheet layout guidelines). Follow TI high-speed ADC layout practice: keep LVDS output pairs at 100-ohm differential impedance, length-matched within 1 mm, and keep analog input traces away from clock and digital switching regions.
Do not leave unused analog inputs floating - terminate per datasheet recommendations to prevent spurs. Configure SNRBoost band selection during firmware bring-up; defaults may not match your IF plan. Verify LVDS timing budget against your FPGA bank's serialization limits at full 200 MSPS before committing the PCB, and confirm the IRGCR ordering suffix matches your required reel quantity.
合規資訊
RoHS/lead-free status per TI standard product offering (IRGCR suffix indicates lead-free finish). REACH and halogen-free status not stated in provided data.
