ADS6443IRGCR - Quad 14-Bit 80-MSPS ADC, Serial LVDS | TI
MPN： ADS6443IRGCR ✓ 啟用中ADS6443IRGCR 概覽
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and converts them into discrete digital codes at a specified sample rate. High-speed pipelined ADCs like the ADS6443 sit in the signal chain between analog front-ends (amplifiers, filters, muxes) and downstream digital processing blocks such as FPGAs, DSPs, or application-specific processors. LVDS-serialized outputs reduce channel count and simplify board routing, which is critical in dense multi-channel systems such as ultrasound, radar, and communications test equipment.
Key features include 14-bit resolution, 80 MSPS maximum sample rate per channel, quadruple simultaneously-sampling channels, serialized LVDS digital interface with one or two lanes per channel, low-latency digital processing, internal references with external-reference option, and programmable gain. According to TI's datasheet, the part maintains spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) suitable for direct-IF and baseband sampling in communications and imaging systems. The wide 80-MSPS operating window plus 14-bit precision makes the device attractive where board area and channel density outweigh absolute peak speed.
The pipelined architecture uses successive low-resolution stages with sample-and-hold between stages, achieving high sample rates without sacrificing bit accuracy. The serialized LVDS output minimizes FPGA pin usage by sending each channel's MSB/LSB data over one or two differential pairs instead of 14 parallel CMOS lines, freeing board area and reducing EMI coupling.
Typical applications include multi-channel ultrasound imaging, communications receiver IF sampling, radar baseband digitization, medical imaging signal chains, phased-array antenna systems, and portable test and measurement instrumentation. When selecting within the ADS644X family, choose the -80 variant for power-sensitive designs and the -125 variant when maximum sample rate is the binding constraint.
直接替換替代品，適用於 ADS6443IRGCR — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS6443IRGCR （相同外形與佔位） — 差異在於 Operating Temperature Range, Package, Number of Channels, Resolution.
ADS6444IRGCT
✅ 直接替換📋 參考替代品（不在目錄中）
ADS6445IRGCT
✅ 直接替換📋 參考替代品（不在目錄中）
ADS6442IRGCR
✅ 直接替換📋 參考替代品（不在目錄中）
ADS6443IRGCT
✅ 直接替換📋 參考替代品（不在目錄中）
ADS6443IRGCR
✅ 直接替換聯絡詢價
查看資料表 →ADS6443IRGCR 最大額定值與電氣特性
| 解析度 | 14 bit |
| Number of Channels | 4 |
| Sample Rate (Max) | 80 MSPS |
| Architecture | Pipelined |
| Digital Output Interface | Serialized LVDS |
| Supply Voltage (AVDD) | 3.3 V |
| Reference Type | Internal (external reference supported) |
| 工作溫度範圍 | -40 C to +85 C |
| 封裝 | 64-VQFN (RGC) 9x9 mm |
| 安裝類型 | Surface Mount |
| Family | ADS644X (125/105/80/65 MSPS variants) |
| Family Speed Variants | ADS6445 (125 MSPS), ADS6444 (105 MSPS), ADS6443 (80 MSPS), ADS6442 (65 MSPS) |
ADS6443IRGCR 64-vqfn (rgc) 9x9 mm 腳位配置指南
ADS6443IRGCR（64-vqfn (rgc) 9x9 mm 封裝）的腳位配置。 此類比元件具有輸入、輸出與電源腳位。偏移歸零、補償與致能腳位配置請參閱製造商資料表。適用於訊號調理與放大器電路。
無詳細腳位定義資料： ADS6443IRGCR.
請參閱 資料表 以查看完整腳位配置。
典型應用
ADS6443IRGCR 適用於 6 應用s: Multi-Channel Ultrasound Imaging Front-End, Communications Receiver IF Sampling, Phased-Array Radar Baseband Digitization, Portable Test & Measurement Instrumentation, Multi-Channel Data Acquisition Systems, Medical Imaging (CT, PET Front-End Digitization).
Multi-Channel Ultrasound Imaging Front-End
The ADS6443IRGCR is well-suited for ultrasound imaging front-ends where four simultaneously-sampling 14-bit channels at 80 MSPS deliver the dynamic range needed to digitize echoes from piezoelectric transducers. Its serialized LVDS output interface drops the FPGA pin count from 56 CMOS lines (14-bit x 4 channels) to roughly 8 differential pairs, simplifying the cabling between the transducer board and the back-end image processor. With 80 MSPS per channel, the part provides more than 2x Nyquist headroom for the typical 5-30 MHz ultrasound band. Designers commonly pair the ADS6443 with TI's THS4631 low-noise op-amp for the LNA/TGC stage and an FPGA implementing beamforming, all on a compact PC board where the QFN-64 footprint's thermal pad aids heat removal.
推薦
Communications Receiver IF Sampling
In communications receivers, the ADS6443IRGCR can directly digitize IF signals in the 70 MHz region at 80 MSPS, allowing software-defined radio (SDR) architectures that push demodulation into firmware. The 14-bit dynamic range supports the high-order modulations (e.g., 64-QAM) used in cellular and point-to-point links, while the four channels enable multi-band or diversity receivers on a single board. The serialized LVDS interface minimizes routing into FPGAs that perform DDC and channelization, keeping the analog front-end isolated from digital noise. Used in conjunction with a bandpass SAW filter and a TI LMH6517 variable-gain amplifier, the ADS6443 forms a flexible IF-sampling chain for test and commercial receiver platforms.
推薦
Phased-Array Radar Baseband Digitization
Phased-array radar systems digitize multiple antenna channels simultaneously to enable digital beamforming, and the ADS6443IRGCR's four channels at 80 MSPS capture pulse-compressed I/Q baseband from a 4-element sub-array. The 14-bit resolution preserves the dynamic range needed to detect small targets in clutter, while serialized LVDS output reduces the board-to-FPGA cabling so each tile in the array stays compact. The -40 C to +85 C industrial temperature range supports outdoor or unmanned-aerial radar installations. Pair with TI's LMX2615 synthesizer for LO and a Kintex-7 FPGA for back-end processing where the QFN-64 footprint aligns with standard radar mezzanine layouts.
推薦
Portable Test & Measurement Instrumentation
Portable oscilloscopes, spectrum analyzers, and arbitrary waveform generators require high channel density without sacrificing sample rate, and the ADS6443IRGCR delivers 80 MSPS on four channels from a single QFN-64 IC. The serialized LVDS output keeps multi-channel triggering manageable inside the instrument chassis, while the 3.3 V analog supply simplifies USB- or battery-powered design budgets. Combined with a TI OPA695 wideband op-amp front-end and an FPGA with on-chip transceivers, the ADS6443 enables pocket-sized four-channel digitizers that compete with benchtop box instruments at a fraction of the cost.
推薦
Multi-Channel Data Acquisition Systems
The ADS6443IRGCR suits industrial data-acquisition systems such as vibration monitoring, sonar, and multi-axis inertial measurement where four high-resolution simultaneously-sampled channels are required on one PCB. The 80-MSPS per-channel rate captures transient events with fine time resolution, while the 14-bit depth retains SNR through long cable runs when paired with a TI THS4521 differential driver front-end. The industrial -40 C to +85 C range tolerates factory-floor cabinet placement, and the QFN-64 package's exposed pad simplifies thermal management in sealed enclosures.
推薦
Medical Imaging (CT, PET Front-End Digitization)
In CT scanners and PET detector front-ends, the ADS6443IRGCR's four channels at 80 MSPS can be grouped to digitize photodetector arrays with reduced FPGA IO overhead. The 14-bit resolution preserves low-contrast resolution required for small-lesion detection in CT slices, while serialized LVDS keeps the dense detector-array PCBs routable. The exposed-pad QFN-64 aids thermal removal when the front-end is stacked behind the detector array, and the internal reference (with external override) simplifies field calibration. Typical designs pair this ADC with a TI LMH6629 ultra-low-noise preamp and a Kintex/Kintex UltraScale FPGA for image reconstruction.
推薦
推薦產品摘要
工程參考資料，適用於 ADS6443IRGCR — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS6444IRGCT | ADS6445IRGCT | ADS6442IRGCR | ADS6443IRGCT |
|---|---|---|---|---|---|
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Number of Channels | 4 | 4 | 4 | 4 | 4 |
| Maximum Sample Rate | 80 MSPS | 105 MSPS | 125 MSPS | 65 MSPS | 80 MSPS |
| Digital Output Interface | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS | Serialized LVDS |
| Supply Voltage (AVDD) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature Range | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
主要差異化特點
- Lowest-power member of ADS644X quad LVDS family (對比ADS6445IRGCT (125 MSPS))
- Same QFN-64 (RGC) 9x9 mm footprint as the entire ADS644X family (對比ADS6444IRGCT and ADS6445IRGCT)
- Serialized LVDS minimizes FPGA pin count (對比CMOS-output ADCs (e.g. parallel-output ADCs without LVDS))
設計說明
Use a separate analog ground (AGND) and digital ground (DGND) plane tied under one point near the ADS6443 to prevent digital return currents from coupling into the analog input pins. Place the input coupling capacitors and reference bypass caps (typically 0.1 uF ceramic + 10 uF tantalum) as close as possible to the part's AVDD and AVDD_REF pins. The exposed thermal pad must be soldered to a continuous ground-copper pour with thermal vias (typically 5-9) to keep junction temperature within derating; this is critical because LVDS drivers and input buffers push the IC's power dissipation into the 1-1.5 W range at 80 MSPS.
Route each channel's analog inputs as a 100-ohm differential pair from the ADC driver op-amp to the ADS6443 input pins, keeping the pair length-matched to within 0.5 mm to preserve SFDR. Clock the ADC with a low-jitter, differential source (e.g., LVC-PECL from a CDCM7005 or LMK03806) because aperture-jitter of just 1 ps can degrade SNR by 1-2 dB at 80 MSPS with 70-MHz IF inputs per the TI datasheet. Keep LVDS output pairs length-matched and routed on 100-ohm differential impedance to the FPGA, with series 100-ohm termination at the receiver.
Do not exceed the maximum sample rate (80 MSPS) or overshoot the absolute-maximum AVDD supply (3.6 V) - using 3.3 V +/-5% is mandatory. Ensure the LVDS output mode (1-lane vs 2-lane per channel, MSB/LSB first, 2's complement vs offset-binary) is configured correctly in the SPI/parallel control registers BEFORE issuing a reset; otherwise the FPGA deserializer will see garbage on first power-up. Decouple the digital DVDD pin even if digital load is light, since switching transients on LVDS edges can inject noise into the analog band. Finally, leave the unused ADC input channels tied to midscale through 1 kohm if they are not driven to avoid internal reference drift effects, per the TI reference schematics.
合規資訊
Compliance information not present in the provided Verified Web Data - marked unknown pending datasheet confirmation.
