ADS8406IPFBTG4 - 16-Bit 1.25MSPS SAR ADC | Texas Instruments
MPN： ADS8406IPFBTG4 ✓ 啟用中ADS8406IPFBTG4 概覽
An SAR ADC is a type of analog-to-digital converter that performs a binary search across an internal capacitive DAC in N clock cycles, producing one conversion per cycle with no pipeline latency. Compared with delta-sigma or pipelined ADCs, SAR converters are valued for deterministic latency, low power, and excellent behavior on multiplexed or single-shot inputs, making them a workhorse in industrial instrumentation. The ADS8406 belongs to TI's broad precision-SAR family, sitting between low-speed 16-bit audio ADCs and high-speed 14/16-bit pipeline parts.
Key features include 16-bit resolution with no missing codes, a 1.25 MHz maximum sample rate, a fully differential pseudo-bipolar input supporting ±2*VREF or 0-4*VREF ranges, a low conversion time around 650 ns, and an internal 4.096 V reference that simplifies BOM. The 48-TQFP package exposes a standard parallel interface that can be configured as a single 16-bit read or two 8-bit cycles, easing connection to 8-bit microcontrollers and DSPs. Typical INL is around +/-2 LSB and SINAD exceeds 85 dB at lower input frequencies.
Typical applications include industrial process control and PLC analog input modules, optical-module bias control, multi-channel data-acquisition front ends, medical instrumentation such as patient monitoring, and precision weigh scales or strain-gauge signal chains. The combination of a 1.25 MSPS throughput and low 35 mW typical dissipation lets the part serve both multiplexed and continuous-stream designs.
When designing with the ADS8406, use a low-impedance RC network at the analog input and decouple AVDD/DRVDD with 1 uF and 100 nF ceramic capacitors placed within 5 mm of the supply pins. Keep the parallel bus short and series-terminate at the driver to avoid digital coupling into the analog input. The internal 4.096 V reference can be bypassed for an external reference if higher accuracy is required.
This page synthesizes distributor pricing, drop-in alternatives from the ADS840x and ADS841x family, and practical design notes not collected in the TI datasheet alone.
直接替換替代品，適用於 ADS8406IPFBTG4 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS8406IPFBTG4 （相同外形與佔位） — 差異在於 Conversion Time, Operating Temperature Range, Package, Architecture, Input Type.
ADS8406IPFBRG4
✅ 直接替換聯絡詢價
查看資料表 →ADS8406IBPFBTG4
✅ 直接替換📋 參考替代品（不在目錄中）
ADS8406IPFBRG4
✅ 直接替換聯絡詢價
查看資料表 →ADS8406IBPFBR
✅ 直接替換📋 參考替代品（不在目錄中）
ADS8406IPFBT
✅ 直接替換📋 參考替代品（不在目錄中）
ADS8401IPFBRG4
✅ 直接替換聯絡詢價
查看資料表 →ADS8406IPFBTG4 最大額定值與電氣特性
| 解析度 | 16 bit |
| Sample Rate | 1.25 MSPS |
| Architecture | SAR (Successive Approximation Register) |
| Number of Channels | 1 |
| Input Type | Pseudo-Bipolar, Fully Differential |
| Internal Reference Voltage | 4.096 V |
| Data Interface | Parallel (16-bit or 8-bit bus) |
| Conversion Time | 650 ns (typ) |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 3 V or 5 V |
| Power Dissipation (typ) | 35 mW |
| 工作溫度範圍 | -40C to +85C (Industrial) |
| 封裝 | 48-TQFP (7x7 mm) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
| Lead-Free | Yes |
ADS8406IPFBTG4 腳位配置
| 腳位 1 | AVDD — Analog supply, 5V |
| 腳位 2 | INP — Positive analog input |
| 腳位 3 | INN — Negative analog input |
| 腳位 4 | AGND — Analog ground |
| 腳位 5 | REF — Reference I/O |
| 腳位 6 | REFCAP — Reference bypass capacitor |
| 腳位 7 | BYPAS — Internal bias bypass |
| 腳位 8 | AGND — Analog ground |
| 腳位 9 | AVDD — Analog supply, 5V |
| 腳位 10 | CS — Chip select, active low |
| 腳位 11 | RD — Read input, active low |
| 腳位 12 | BUSY — Conversion in progress, active high |
| 腳位 13 | DRVDD — Digital I/O supply |
| 腳位 14 | DRGND — Digital ground |
| 腳位 15 | CONVST — Conversion start input |
| 腳位 16 | RANGE — Input range select |
| 腳位 17 | BYTE — Byte/parallel mode select |
| 腳位 18 | RESET — Reset input |
| 腳位 19 | NC — Not connected (per datasheet) |
| 腳位 20 | D0 — Data bit 0 (LSB) |
| 腳位 21 | D1 — Data bit 1 |
| 腳位 22 | D2 — Data bit 2 |
| 腳位 23 | D3 — Data bit 3 |
| 腳位 24 | D4 — Data bit 4 |
| 腳位 25 | D5 — Data bit 5 |
| 腳位 26 | D6 — Data bit 6 |
| 腳位 27 | D7 — Data bit 7 |
| 腳位 28 | D8 — Data bit 8 |
| 腳位 29 | D9 — Data bit 9 |
| 腳位 30 | D10 — Data bit 10 |
| 腳位 31 | D11 — Data bit 11 |
| 腳位 32 | D12 — Data bit 12 |
| 腳位 33 | D13 — Data bit 13 |
| 腳位 34 | D14 — Data bit 14 |
| 腳位 35 | D15 — Data bit 15 (MSB) |
| 腳位 36 | DRGND — Digital ground |
| 腳位 37 | DRVDD — Digital I/O supply |
| 腳位 38 | TAG — Tag input for output bit |
| 腳位 39 | NC — Not connected (per datasheet) |
| 腳位 40 | NC — Not connected (per datasheet) |
| 腳位 41 | AGND — Analog ground |
| 腳位 42 | REFGND — Reference ground |
| 腳位 43 | REF — Reference I/O |
| 腳位 44 | AGND — Analog ground |
| 腳位 45 | AVDD — Analog supply, 5V |
| 腳位 46 | AVDD — Analog supply, 5V |
| 腳位 47 | AGND — Analog ground |
| 腳位 48 | NC — Not connected (per datasheet) |
典型應用
ADS8406IPFBTG4 適用於 6 應用s: Industrial Process Control / PLC Analog Input, Precision Weigh Scales and Strain-Gauge Signal Chains, Optical Module Bias Control, Multi-Channel Data Acquisition Front End, Medical Patient Monitoring, Test and Measurement Instrumentation.
Industrial Process Control / PLC Analog Input
The ADS8406's 1.25 MSPS throughput and 16-bit no-missing-codes resolution make it well matched to PLC analog input modules that scan multiple sensors rapidly. Its fully differential pseudo-bipolar input rejects common-mode noise from long field wiring, while the internal 4.096 V reference removes the need for an external precision reference in cost-sensitive designs. Place 1 uF and 100 nF ceramic bypass capacitors on AVDD within 5 mm of the pins, and use a 20 ohm RC at the analog input to limit charge-kickback. The parallel interface simplifies connection to industrial Cortex-M or DSP controllers that lack high-speed serial ports, while 35 mW typical dissipation enables 8-channel multiplexed front ends without exceeding thermal budgets.
推薦
Precision Weigh Scales and Strain-Gauge Signal Chains
Weigh scales require 16-bit or higher resolution to capture sub-gram load cell changes, and the ADS8406 delivers true 16-bit performance with the 4.096 V internal reference simplifying ratiometric measurement of a bridge excited near 4.096 V. Its low integral non-linearity directly translates to a wide dynamic range that supports both small and large loads on the same load cell. The differential input rejects thermocouple and power-line noise picked up by long cables, and the 35 mW dissipation keeps the analog front end thermally quiet, which is critical for strain-gauge stability. Use a low-noise op-amp such as the OPA227 as an input buffer to maintain full-scale accuracy across the operating temperature range.
推薦
Optical Module Bias Control
Optical transceivers and LiDAR receivers need closed-loop control of laser bias and modulation currents, where a fast and accurate ADC is required to digitize monitor photodiode currents. The 1.25 MSPS speed of the ADS8406 easily tracks a 10 kHz control loop while leaving margin for housekeeping channels. The pseudo-bipolar differential input directly digitizes photodiode currents biased near mid-rail, eliminating the need for a transimpedance front end with bipolar supplies. The internal 4.096 V reference is stable enough for set-and-forget bias calibration, and the parallel interface can be shared with an FPGA host that handles modulation and clocking in a single chip.
推薦
Multi-Channel Data Acquisition Front End
Multi-channel DAQ systems for vibration, seismic, or sonar front-end digitizers benefit from the deterministic single-cycle latency of the ADS8406. The 1.25 MSPS throughput per channel allows 8 channels to be time-multiplexed at 156 kSPS per channel with full 16-bit accuracy, and the low aperture delay makes channel-to-channel phase matching trivial. The 48-TQFP footprint keeps board area small, leaving room for a per-channel input multiplexer and antialias filter. Driving the parallel bus directly into an FPGA FIFO enables continuous streaming to memory with zero host-CPU overhead, ideal for capturing transient events in the field.
推薦
Medical Patient Monitoring
Patient monitors for ECG, SpO2, and invasive blood pressure all require 16-bit analog front ends to capture small biopotential signals below 1 mV with sufficient dynamic range. The ADS8406's differential input rejects 50/60 Hz mains pickup from long patient leads when paired with a right-leg drive circuit, and the internal 4.096 V reference simplifies IEC 60601-1 calibration. The 35 mW dissipation keeps the analog section cool, important when the monitor is worn on the body or used near sensitive skin electrodes. The parallel interface connects to a Cortex-M4 host that runs the display and the safety-critical alarm algorithms in a single chip.
推薦
Test and Measurement Instrumentation
Bench-top oscilloscopes, power analyzers, and arbitrary waveform generators all use 16-bit ADCs to characterize analog signals. The 1.25 MSPS throughput of the ADS8406 covers audio-band and slow-RF test signals comfortably, while its 16-bit resolution enables better than 0.005% full-scale measurement accuracy. The pseudo-bipolar input directly digitizes signals swinging around ground without the extra level-shift circuit required by single-supply ADCs, and the parallel data bus can be captured directly by an FPGA or a high-speed DSP for FFT and THD analysis. The 48-TQFP package also has good thermal dissipation for the long acquisition sessions typical in automated test.
推薦
推薦產品摘要
工程參考資料，適用於 ADS8406IPFBTG4 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS8406IPFBRG4 | ADS8406IBPFBTG4 | ADS8406IPFBR | ADS8401IPFBRG4 |
|---|---|---|---|---|---|
| Package | 48-TQFP (7x7) | 48-TQFP (7x7) | 48-TQFP (7x7) | 48-TQFP (7x7) | 48-TQFP (7x7) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 12 bit |
| Sample Rate | 1.25 MSPS | 1.25 MSPS | 1.25 MSPS | 1.25 MSPS | 1.25 MSPS |
| Architecture | SAR | SAR | SAR | SAR | SAR |
| Input Type | Pseudo-Bipolar, Fully Differential | Pseudo-Bipolar, Fully Differential | Pseudo-Bipolar, Fully Differential | Pseudo-Bipolar, Fully Differential | Pseudo-Bipolar, Fully Differential |
| Internal Reference | 4.096 V | 4.096 V | 4.096 V | 4.096 V | 4.096 V |
| Data Interface | Parallel (16/8-bit) | Parallel (16/8-bit) | Parallel (16/8-bit) | Parallel (16/8-bit) | Parallel (16/8-bit) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Higher resolution than 12-bit predecessors in same package (對比ADS8401IPFBRG4)
- Industrial-screen variant for harsh environments (對比ADS8406IPFBRG4)
- Internal 4.096 V reference eliminates external reference BOM (對比ADS8383IPFBTG4)
設計說明
Decouple AVDD and DRVDD with 1 uF and 100 nF ceramic capacitors placed within 5 mm of the supply pins. The ADS8406 draws roughly 35 mW typical at 1.25 MSPS from a 5 V analog supply; use a star-ground topology to keep digital return currents from polluting the analog ground. Estimated: total quiescent current at full speed is approximately 7 mA from 5 V AVDD and 1 mA from 3.3 V DRVDD, based on the typical 35 mW analog power figure from the datasheet.
The ADS8406 parallel output bus toggles all 16 data lines plus CS, RD, BUSY and TAG on every conversion, producing high-frequency noise. Series-terminate each output with 20-33 ohm resistors to dampen reflections, and place the bus traces over a continuous ground plane to limit crosstalk. Keep the analog input traces short and symmetric, with a 20 ohm series resistor and a 1 nF-10 nF capacitor at the input pin to form a charge-kickback filter.
Do not operate the ADS8406 without the REFCAP and BYPAS capacitors in place; the internal 4.096 V reference and bias circuits need the external caps to meet linearity spec. Reading the ADC during the BUSY high period yields incorrect data, so gate RD with BUSY or use the falling edge as a hardware interrupt. The RANGE input must be tied to a known logic level, not left floating, or input range selection becomes indeterminate. Estimated: with REFCAP = 10 uF and BYPAS = 1 uF, the reference settles in roughly 10 ms after power-up.
The 48-TQFP package has a theta_JA of approximately 70 C/W on a standard 4-layer JEDEC test board. At 35 mW typical dissipation the self-heating is well under 1 C, so thermal management is not a concern for the standard grade. If you operate the part at maximum sample rate continuously, add 100 mm^2 of top-side copper over the AVDD and AGND pins to keep junction rise below 5 C. Estimated: junction-to-ambient rise is approximately 70 C/W * 0.035 W = 2.45 C with the minimum copper footprint.
合規資訊
RoHS and REACH compliance per TI product page. The ADS8406IPFBTG4 is Pb-free and supplied on tape and reel. AEC-Q100 not qualified - this is an industrial-grade (-40C to +85C) part, not automotive.
