CD4046BF - CMOS Micropower Phase-Locked Loop | Texas Instruments
MPN： CD4046BF ✓ 啟用中CD4046BF 概覽
A phase-locked loop is a feedback-control system in which an internal voltage-controlled oscillator is adjusted until its output frequency or phase agrees with a reference input. In the CD4046BF, the signal-input amplifier feeds the selected phase-comparator path, while the VCO provides the tunable output. The PLL can therefore compare an incoming reference against a divided or generated frequency and present an error voltage for loop filtering and frequency control. The loop filter is external, allowing designers to tune loop bandwidth, capture behavior, damping, and output jitter according to the application.
The key features of the CD4046BF are its 3 V to 18 V supply range, micropower CMOS operation, integrated VCO, two phase comparators, and broad -55 C to +125 C temperature rating. The VCO is linear, making the output frequency controllable by an external voltage. The common input amplifier and comparator input simplify use with external frequency-divider and loop-filter networks. The CD4046BF is a useful building block when a system needs both frequency synthesis and flexible feedback-loop implementation rather than a fixed-frequency oscillator.
The device uses analog control techniques around a CMOS digital-compatible integrated circuit. The VCO output frequency depends on its control voltage and external timing components, while the phase comparator converts phase or frequency differences into an error signal. Designers should account for comparator type, loop-filter transfer function, VCO gain, divider ratio, reference frequency, and component tolerances. In practical designs, a low-pass filter commonly connects the comparator output to the VCO control input, and a frequency divider may be inserted between the VCO output and comparator input when integer multiplication is required.
Typical applications include FM and AM demodulation, tone decoding, frequency synthesis, frequency multiplication, frequency division, phase discrimination, motor-speed-related modulation, communications interfaces, and instrumentation. The 16-CDIP package is particularly useful where through-hole assembly, rugged mechanical construction, or a wide temperature range is preferred over a surface-mount footprint. Designers should confirm timing, output-drive, supply-current, and component-temperature requirements against the manufacturer datasheet before production release.
The most important design consideration is selecting the correct comparator and calculating the loop filter around the intended reference frequency. A filter that is too aggressive can increase noise or slow acquisition, while an insufficiently filtered loop can jitter or oscillate. Keep the VCO timing components and sensitive comparator nodes away from noisy switching paths, use a stable low-noise control voltage, and check the maximum operating frequency for the selected external components. The CD4046BF is not a power semiconductor, so a safe operating area specification is not applicable.
直接替換替代品，適用於 CD4046BF — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： CD4046BF （相同外形與佔位） — 差異在於 Mounting Type, Package, Product Type.
CD4046BE
✅ 直接替換聯絡詢價
查看資料表 →MC14046B
✅ 直接替換📋 參考替代品（不在目錄中）
HEC4046B
✅ 直接替換📋 參考替代品（不在目錄中）
HEF4046B
✅ 直接替換📋 參考替代品（不在目錄中）
CD4046BF 規格
| Product Type | CMOS micropower phase-locked loop (PLL) |
| Supply Voltage Range | 3 V to 18 V |
| Maximum Frequency | 2.4 MHz |
| 工作溫度範圍 | -55 C to +125 C |
| VCO Type | Low-power linear voltage-controlled oscillator |
| Phase Comparator Count | 2 |
| Common Input Amplifier | 1 |
| Common Comparator Input | 1 |
| 封裝 | 16-lead CDIP |
| 安裝類型 | Through-hole |
| Logic Family | CMOS |
| Datasheet Page Count | 16 pages |
| Supplier Price as of 2026-10-23 | From $30.1173 |
| Supplier Availability as of 2026-10-23 | In stock at LCSC |
| Input Signal | Signal input through common amplifier |
| Output Function | Frequency synthesis and phase-locked control |
| SOA | Not applicable |
CD4046BF 16-lead cdip 腳位配置指南
CD4046BF（16-lead cdip 封裝）的腳位配置。 腳位編號、功能與連接圖定義於製造商資料手冊中。請參閱該手冊以取得確切的封裝尺寸與焊接指引。
無詳細腳位定義資料： CD4046BF.
請參閱 資料表 以查看完整腳位配置。
典型應用
CD4046BF 適用於 6 應用s: FM Demodulation, Frequency Synthesis, Tone Decoding, Frequency Division and Multiplication, Communications and Modulation Interfaces, Industrial Control and Instrumentation.
FM Demodulation
The CD4046BF is suited to FM demodulation because its VCO and phase comparator form a feedback loop that can track an incoming carrier while an external loop filter sets the bandwidth. With a 3 V to 18 V supply and operation up to 2.4 MHz under the verified conditions, the device can serve low-frequency and instrumentation-style demodulation circuits. The designer must select the comparator mode, calculate the loop filter, and verify capture range and linearity with the actual carrier frequency. External timing components set the VCO operating point, while the filter removes high-frequency error components and determines audio or data bandwidth. Because the 16-CDIP package is through-hole, it is useful for prototypes, industrial equipment, and repair or legacy-system designs.
推薦
Frequency Synthesis
CD4046BF can implement a programmable frequency synthesizer by comparing a stable reference with a divided VCO output. The VCO control voltage sets the generated frequency, and the phase comparator drives an external loop filter that corrects phase and frequency error. The 3 V to 18 V supply range supports integration into CMOS-compatible control systems, while the verified maximum frequency of 2.4 MHz provides a useful ceiling for many low- and mid-frequency designs. A frequency divider between the VCO output and comparator input enables integer multiplication relationships. Timing-component tolerance, loop stability, reference jitter, and settling time should be evaluated together rather than optimizing only the nominal carrier frequency.
推薦
Tone Decoding
The CD4046BF is useful for tone decoding because the PLL can lock to a selected audio-frequency or communications tone and provide a control signal when the input frequency falls within the designed capture range. The external loop filter determines how quickly the decoder responds and how broadly it accepts frequencies near the target. Designers should calculate the VCO frequency range from the timing network, account for comparator choice, and test temperature and supply variation. The 16-CDIP package supports through-hole assembly in alarm panels, tone-based control systems, and legacy communications equipment. The main design trade-off is between a narrow, selective filter and a wider filter with faster acquisition or greater susceptibility to adjacent-tone errors.
推薦
Frequency Division and Multiplication
CD4046BF can support frequency division or multiplication when a counter or divider is placed in the feedback path between the VCO output and the phase comparator. The loop then drives the VCO until the divided output agrees with the reference, allowing the VCO output to operate at a controlled multiple of the reference frequency. This architecture is useful in frequency standards, clock-generation modules, and legacy communications equipment. The external divider ratio, loop filter, and VCO timing network must be designed together to maintain capture margin and suppress false locks. The 3 V to 18 V supply range and -55 C to +125 C rating make temperature behavior an important verification item, especially when component tolerances or VCO gain vary across the operating range.
推薦
Communications and Modulation Interfaces
CD4046BF is applicable to communications and modulation interfaces where a received frequency must be tracked, filtered, or translated into a stable control voltage. The phase comparator converts phase or frequency error into a feedback signal, and the VCO supplies the adjustable local oscillator. With operation from 3 V to 18 V, the device fits systems that combine CMOS control logic with analog signal conditioning. The design should verify input amplitude limits, comparator mode, loop bandwidth, and output loading against the manufacturer datasheet. The 16-CDIP package makes it practical for through-hole industrial communications equipment, laboratory instruments, and repair platforms where a surface-mount redesign is undesirable. External filtering is essential for controlling modulation bandwidth and rejecting unwanted frequency components.
推薦
Industrial Control and Instrumentation
CD4046BF can serve industrial control and instrumentation systems that need closed-loop frequency regulation, phase comparison, or synchronous reference generation. Its -55 C to +125 C operating-temperature rating is particularly useful where equipment must operate across a broad environmental range, subject to component-level derating and verified test requirements. The VCO and phase comparators provide flexible analog feedback around an external loop filter and divider. In practice, the circuit can generate a control voltage proportional to frequency deviation, lock a local oscillator to an external reference, or support measurement systems that need stable frequency relationships. Keep sensitive timing and comparator nodes away from switching-power nodes, use stable reference components, and validate lock range and timing margin at the expected supply tolerances.
推薦
推薦產品摘要
工程參考資料，適用於 CD4046BF — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | CD4046BE | MC14046B | HEC4046B | HEF4046B | CD4046BNSR |
|---|---|---|---|---|---|---|
| Package | 16-CDIP | 16-CDIP candidate | 16-CDIP candidate | 16-CDIP candidate | 16-CDIP candidate | 16-SOP candidate; not a physical drop-in |
| Brand | Texas Instruments | Texas Instruments | onsemi | Signetics | Signetics | Texas Instruments |
主要差異化特點
- Broad temperature-rated 16-CDIP implementation (對比CD4046BE)
- Integrated dual phase-comparator architecture (對比MC14046B)
- Through-hole CD4046BF construction (對比CD4046BNSR)
設計說明
Keep the VCO timing network, phase-comparator inputs, and loop-filter components close to the CD4046BF and away from switching regulators, high-current return paths, and long unprotected traces. The PLL can amplify delay and noise through its feedback loop, so route the comparator and VCO-control nets as short, quiet analog paths. Use a solid ground reference and keep external divider outputs away from the reference-input node where possible.
Design the external loop filter around the intended reference frequency and VCO gain rather than selecting a generic capacitor value. The CD4046BF’s PLL response depends on comparator type, VCO control sensitivity, divider ratio, and phase margin. Verify startup, capture, lock range, and settling across the 3 V to 18 V supply range. Do not infer current consumption or timing limits from the distributor listing; use the manufacturer datasheet.
Do not treat a 4046-family PLL as a drop-in solely because the function is similar. Confirm every pin, the comparator mode, VCO frequency range, supply limits, output loading, temperature grade, and package drawing. The verified comparison identifies CD4046BE as a possible equivalent, but the supplied data does not establish every operating parameter. Validate lock behavior in hardware before releasing a replacement to production.
合規資訊
The supplied verified data does not include explicit RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals statements. The component is presented as an integrated circuit, so SOA is not applicable.
