DS90LV018ATM - 400 Mbps LVDS Receiver | Texas Instruments
MPN： DS90LV018ATM ✓ 啟用中DS90LV018ATM 概覽
An LVDS receiver is an interface IC that recovers a digital signal carried by two low-voltage differential conductors. LVDS belongs to the differential data-interface hierarchy, where the voltage difference between the pair carries the information while common-mode voltage rejection helps limit noise pickup. The DS90LV018A therefore belongs to the broader interface IC category, where it sits between a physical data link and the CMOS logic, processor, serializer, or test equipment receiving the recovered data.
The device supports data rates in excess of 400 Mbps, or 200 MHz, while maintaining a typical differential input sensitivity of 350 mV. According to the Texas Instruments DS90LV018A datasheet, the receiver converts the differential LVDS input into 3 V CMOS output levels. It also supports open, shorted, and 100-ohm terminated-input fail-safe conditions, with the receiver output remaining HIGH in every specified fail-safe condition.
The flow-through pin arrangement simplifies routing between the LVDS input connector or transceiver and the receiving digital circuitry. Its CMOS interface allows direct connection to compatible TTL or CMOS logic domains when voltage and timing requirements are satisfied. The architecture is intended for systems needing low power consumption and low noise without the complexity of a general-purpose differential receiver with programmable controls. The 8-pin SOIC outline also supports conventional surface-mount PCB assembly.
Typical uses include industrial control links, test and measurement equipment, computer peripherals, video or imaging interfaces, and communication equipment operating over balanced cables. The receiver is especially useful where the transmitter produces an LVDS signal over a cable or PCB trace and the destination requires a single-ended CMOS result. System timing should still be evaluated across the complete transmitter, channel, receiver, and downstream logic path.
When laying out the receiver, place input and output decoupling capacitors close to their associated power pins and keep the differential route compact, symmetrical, and away from noisy switching nodes. Use controlled-impedance routing where the interconnect behaves as a transmission line, and follow the datasheet's recommended termination arrangement for the source and receiver configuration. Verify signal integrity at the target data rate rather than relying only on a maximum-rate headline specification.
This product page combines the manufacturer's core operating specifications, same-package replacement guidance, application-specific engineering guidance, and a parameter-by-parameter comparison. It is intended to shorten receiver selection while preserving the package, interface, and fail-safe details that determine whether an LVDS link can be deployed reliably.
直接替換替代品，適用於 DS90LV018ATM — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： DS90LV018ATM （相同外形與佔位） — 差異在於 Package, Supply Voltage, Maximum Data Rate, Product Type, RoHS Status.
DS90LV018ATM/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
DS90LV018ATMX/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
DS90LV017ATM/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
DS90LV019ATM/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
SN65HVD230DR
✅ 直接替換聯絡詢價
查看資料表 →SN65LVDS93ADGGR
✅ 直接替換聯絡詢價
查看資料表 →DS90LV018ATM 規格
| Product Type | LVDS single differential line receiver |
| Logic Family | CMOS |
| 供應電壓 | 3 V |
| Maximum Data Rate | Greater than 400 Mbps |
| 最大時脈頻率 | 200 MHz |
| Typical Differential Input Voltage | 350 mV |
| Output Logic Level | 3 V CMOS |
| Propagation Delay | 1.5 ns |
| 靜態電流 | 9 mA |
| 工作溫度範圍 | -40 °C to +85 °C |
| 封裝 | 8-pin SOIC |
| 安裝類型 | Surface mount |
| Fail-Safe Input Support | Open, shorted, and 100 Ω terminated inputs |
| Fail-Safe Output State | HIGH |
| PCB Layout Style | Flow-through |
DS90LV018ATM 8-pin soic 腳位配置指南
DS90LV018ATM（8-pin soic 封裝）的腳位配置。 腳位編號、功能與連接圖定義於製造商資料手冊中。請參閱該手冊以取得確切的封裝尺寸與焊接指引。
無詳細腳位定義資料： DS90LV018ATM.
請參閱 資料表 以查看完整腳位配置。
典型應用
DS90LV018ATM 適用於 6 應用s: Industrial Control Data Links, Test and Measurement Equipment, Computer Peripherals, Video and Imaging Interfaces, Communication Equipment, Low-Power Distributed Sensors.
Industrial Control Data Links
The DS90LV018ATM is appropriate for industrial balanced data links that require a 3 V CMOS result from an LVDS pair. Its data-rate capability above 400 Mbps provides margin for machine-control, remote I/O, and high-speed sensor-interface traffic, while 9 mA quiescent current supports power-constrained distributed equipment. The receiver's open, shorted, and 100 Ω terminated-input fail-safe support also helps define behavior when a cable or connector faults. Engineers should still validate timing through the complete transmitter, cable, connector, receiver, and controller path because the headline rate alone does not establish end-to-end eye margin.
推薦
Test and Measurement Equipment
The DS90LV018ATM can recover high-speed differential test signals while presenting a 3 V CMOS output to counters, logic analyzers, or acquisition hardware. Its propagation delay of 1.5 ns and support for rates above 400 Mbps make it useful where cable losses and skew must be tolerated without immediately converting the signal to single-ended logic too early. The 8-pin SOIC package also supports compact instrument PCBs. Timing calibration should include the receiver delay, source timing, cable propagation, and instrument input characteristics, especially when measuring low-jitter or high-throughput interfaces.
推薦
Computer Peripherals
The DS90LV018ATM suits computer peripherals and point-to-point workstation links that use LVDS over a short cable or controlled PCB connection. The receiver translates a typical 350 mV differential signal into a 3 V CMOS logic level, allowing the result to feed compatible digital circuitry without a full transceiver. Low 9 mA quiescent current and operation across -40 °C to +85 °C support equipment intended for controlled industrial or commercial environments. Designers should compare the companion transmitter's output amplitude and timing with the receiver's threshold, then validate connector and cable behavior at the intended rate.
推薦
Video and Imaging Interfaces
The DS90LV018ATM can serve as the receive endpoint for balanced links carrying high-rate data between imaging, display, or processing modules. Converting the LVDS pair to 3 V CMOS locally provides a conventional logic interface for downstream digital circuitry, while data rates above 400 Mbps accommodate demanding transfer paths. The flow-through package arrangement helps preserve a direct signal route on the PCB. For video designs, evaluate horizontal and vertical video timing, added receiver delay, skew tolerance, and any lane-to-lane alignment requirements rather than treating the part as a general-purpose video encoder or decoder.
推薦
Communication Equipment
The DS90LV018ATM is well suited to communication equipment that uses low-voltage differential signaling for reliable point-to-point transfers. Its typical 350 mV input sensitivity, operation above 400 Mbps, and defined fail-safe behavior support robust receiver-side implementation, while 9 mA quiescent current reduces the burden on compact power systems. The 8-pin SOIC package enables placement near a connector or line-driver stage with a short differential route. Link-budget analysis should include transmitter amplitude, source and receiver termination, cable attenuation, connector reflections, and clock or data recovery behavior at the destination.
推薦
Low-Power Distributed Sensors
The DS90LV018ATM can receive LVDS data from distributed sensors or remote modules where a robust differential link and low receiver dissipation are important. Its 9 mA quiescent current is suitable for systems with limited power budgets, and the single-channel architecture avoids the overhead of a multi-channel device when only one link is required. Inputs from sensors should still comply with the receiver's 3 V supply, typical 350 mV differential signal, and timing constraints. Use twisted-pair routing, maintain a controlled return path, and verify fail-safe behavior when the remote module is disconnected or its driver enters an abnormal state.
推薦
推薦產品摘要
工程參考資料，適用於 DS90LV018ATM — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | DS90LV018ATM/NOPB | DS90LV018ATMX/NOPB | DS90LV017ATM/NOPB | DS90LV019ATM/NOPB | SN65HVD2 | SN65LVDS |
|---|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 8-pin SOIC | 8-pin SOIC - same | 8-pin SOIC - same | 8-pin SOIC - same | 8-pin SOIC - same | 8-pin SOIC - same | 8-pin SOIC - same |
主要差異化特點
- Single-receiver 400 Mbps class with low quiescent current (對比DS90LV017ATM/NOPB)
- Defined fail-safe behavior for multiple fault states (對比SN65HVD2)
- High-speed conversion with compact propagation delay (對比SN65LVDS)
- Closest ordering equivalence for footprint reuse (對比DS90LV018ATMX/NOPB)
設計說明
Route the differential input as a short, symmetric pair with a continuous reference plane. Keep the LVDS traces away from switching inductors, high-current return paths, and unrelated clock or data traces. If the connection is long enough to behave as a transmission line, use the termination arrangement specified by the Texas Instruments DS90LV018A datasheet and avoid adding unaccounted stubs at test points.
Place the receiver close to the connector or LVDS transmitter rather than routing the high-speed differential signal across the PCB before conversion to CMOS. Maintain a consistent impedance through connectors and escape geometry, and avoid changing the pair spacing near package pads. The flow-through arrangement supports direct routing, but its benefits depend on preserving symmetry and minimizing vias in the high-speed path.
Apply the manufacturer-recommended bypass network directly to the 3 V supply pins, using high-frequency ceramic capacitors and placing the smallest capacitor closest to the device. Additional scattered decoupling can help control impedance on larger boards, but it does not replace local supply-pin bypassing. Verify the downstream CMOS load, transmitter current, and power-source impedance before assuming the receiver's 9 mA figure represents total board demand.
Evaluate the complete LVDS link rather than only the receiver datasheet limit. Include source amplitude, source termination, receiver threshold, cable loss, connector transitions, propagation delay, and downstream setup-and-hold timing. A link operating at 400 Mbps has materially less timing margin than the stated greater-than-400-Mbps capability, so use receiver-specific timing and fail-safe behavior to establish whether operation is reliable.
Do not substitute a receiver based only on the words LVDS or the existence of an 8-pin SOIC outline. Verify pin numbers, input polarity, output polarity, enable requirements, supply limits, propagation delay, and fail-safe states against the candidate datasheet. The target's 350 mV typical differential input and HIGH fail-safe output are particularly important when the source cable may be open, shorted, or terminated by 100 Ω.
合規資訊
The manufacturer datasheet and product information describe the electrical function, package, operating range, and fail-safe behavior, but no explicit RoHS, REACH, AEC-Q100, lead-free, halogen-free, or conflict-minerals status was identified.