DSPIC33EP128GS804-I/PT - 16-bit 70MIPS Digital Power DSC | Microchip
MPN： DSPIC33EP128GS804-I/PT ✓ 啟用中DSPIC33EP128GS804-I/PT 概覽
A digital signal controller combines the compute power of a DSP core with the peripherals and ease of use of a microcontroller, sitting between an MCU and a DSP in the embedded hierarchy. DSCs are the standard choice for closed-loop digital control of switch-mode power supplies, where fast deterministic interrupt handling and high-resolution PWM are essential.
The GS804 variant belongs to Microchip's SMPS and Digital Power Conversion family (dsPIC33EPxxGS70x/80x). Its headline features are interconnected high-speed PWM modules with dedicated time bases, a high-speed 10/12-bit ADC with Sample-and-Hold and an integrated Programmable Gain Amplifier (PGA), analog comparators, and two CAN bus modules for industrial communication.
Architecturally, the device couples the dsPIC33E 16-bit core with dual flash partitioning supporting live firmware updates, DMA for low-overhead data movement between ADC, PWM and RAM, and peripheral interconnection that lets comparator and ADC events trigger PWM fault states in hardware without CPU latency - a decisive advantage in power conversion loops.
Typical applications include AC-to-DC converters, power factor correction (PFC) stages, digital DC-DC converters, battery chargers, solar micro-inverters and LED drivers. The CAN interface also makes it suitable for automotive-auxiliary and industrial networking nodes.
Design consideration: the 70 MIPS core runs from a 3.3 V supply, so PWM dead-time resolution and ADC sampling must be budgeted against the control-loop period; use Microchip's Digital Compensator design tools for loop tuning.
This page synthesizes distributor stock data, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
直接替換替代品，適用於 DSPIC33EP128GS804-I/PT — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： DSPIC33EP128GS804-I/PT （相同外形與佔位） — 差異在於 Operating Temperature, Package, RAM, Flash Memory, ADC.
DSPIC33EP256GS804-I/PT
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
DSPIC33EP64GS804-I/PT
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →DSPIC33EP128GS704-I/PT
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →DSPIC33EP128GM304-I/PT
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →DSPIC33EP128GS804-I/PT 最大額定值與電氣特性
| Core | dsPIC33E 16-bit |
| Max CPU Speed | 70 MIPS |
| Flash Memory | 128 KB (43K x 24) |
| RAM | 8 KB |
| 供應電壓 | 3.3 V |
| 封裝 | 44-TQFP (10x10 mm) |
| 安裝類型 | Surface Mount |
| 工作溫度 | -40C to +85C (I-grade) |
| CAN Modules | Yes (CAN featured per distributor data) |
| High-Speed PWM | Interconnected high-speed PWM modules |
| ADC | High-speed ADC with PGA |
| Analog Comparators | Yes |
| Dual Partition Flash | Yes (live firmware update) |
| Application Focus | SMPS and Digital Power Conversion |
| Functional Safety Support | Yes (FuSa variant listed by DigiKey) |
| Packaging | Tray |
DSPIC33EP128GS804-I/PT 腳位配置
| 腳位 1 | MCLR — Master clear reset input |
| 腳位 2 | AN0/RB0 — Analog input 0 / port B bit 0 |
| 腳位 3 | AN1/RB1 — Analog input 1 / port B bit 1 |
| 腳位 4 | AN2/RB2 — Analog input 2 / port B bit 2 |
| 腳位 5 | AN3/RB3 — Analog input 3 / port B bit 3 |
| 腳位 6 | AN4/RB4 — Analog input 4 / port B bit 4 |
| 腳位 7 | AN5/RB5 — Analog input 5 / port B bit 5 |
| 腳位 8 | VSS — Ground reference |
| 腳位 9 | OSC1/CLKI/RC12 — Oscillator crystal input / external clock input |
| 腳位 10 | OSC2/CLKO/RC15 — Oscillator crystal output / clock output |
| 腳位 11 | VDD — Positive supply (3.3 V) |
| 腳位 12 | AN6/RB6 — Analog input 6 / port B bit 6 |
| 腳位 13 | AN7/RB7 — Analog input 7 / port B bit 7 |
| 腳位 14 | AN8/RB8 — Analog input 8 / port B bit 8 |
| 腳位 15 | AN9/RB9 — Analog input 9 / port B bit 9 |
| 腳位 16 | AN10/RB10 — Analog input 10 / port B bit 10 |
| 腳位 17 | AN11/RB11 — Analog input 11 / port B bit 11 |
| 腳位 18 | AN12/RB12 — Analog input 12 / port B bit 12 |
| 腳位 19 | AN13/RB13 — Analog input 13 / port B bit 13 |
| 腳位 20 | VSS — Ground reference |
| 腳位 21 | VDD — Positive supply (3.3 V) |
| 腳位 22 | PGD1/RB14 — In-circuit debug data pin 1 / port B bit 14 |
| 腳位 23 | PGC1/RB15 — In-circuit debug clock pin 1 / port B bit 15 |
| 腳位 24 | AVDD — Analog positive supply |
| 腳位 25 | AVSS — Analog ground |
| 腳位 26 | PWM1L1/RE0 — PWM1 low-side output 1 / port E bit 0 |
| 腳位 27 | PWM1H1/RE1 — PWM1 high-side output 1 / port E bit 1 |
| 腳位 28 | PWM1L2/RE2 — PWM1 low-side output 2 / port E bit 2 |
| 腳位 29 | PWM1H2/RE3 — PWM1 high-side output 2 / port E bit 3 |
| 腳位 30 | PWM1L3/RE4 — PWM1 low-side output 3 / port E bit 4 |
| 腳位 31 | PWM1H3/RE5 — PWM1 high-side output 3 / port E bit 5 |
| 腳位 32 | PWM1L4/RE6 — PWM1 low-side output 4 / port E bit 6 |
| 腳位 33 | PWM1H4/RE7 — PWM1 high-side output 4 / port E bit 7 |
| 腳位 34 | PWM2L1/RD2 — PWM2 low-side output 1 / port D bit 2 |
| 腳位 35 | PWM2H1/RD3 — PWM2 high-side output 1 / port D bit 3 |
| 腳位 36 | PWM2L2/RD4 — PWM2 low-side output 2 / port D bit 4 |
| 腳位 37 | PWM2H2/RD5 — PWM2 high-side output 2 / port D bit 5 |
| 腳位 38 | PWM2L3/RD6 — PWM2 low-side output 3 / port D bit 6 |
| 腳位 39 | PWM2H3/RD7 — PWM2 high-side output 3 / port D bit 7 |
| 腳位 40 | VDD — Positive supply (3.3 V) |
| 腳位 41 | VSS — Ground reference |
| 腳位 42 | C1RX/RC0 — CAN1 receive input / port C bit 0 |
| 腳位 43 | C1TX/RC1 — CAN1 transmit output / port C bit 1 |
| 腳位 44 | PGD2/RF12 — In-circuit debug data pin 2 / port F bit 12 |
典型應用
DSPIC33EP128GS804-I/PT 適用於 6 應用s: AC-DC Power Supplies, Power Factor Correction (PFC), DC-DC Converters (Digital Buck/Boost), Solar Micro-Inverters, Battery Chargers, Digital LED Drivers.
AC-DC Power Supplies
The DSPIC33EP128GS804-I/PT controls offline AC-DC converters where Microchip explicitly targets the GS family at multi-loop digital SMPS. Its interconnected high-speed PWM generates phase-shifted or complementary drive pairs with hardware fault shutdown, while the high-speed ADC with PGA samples output voltage and input current with the resolution needed for tight regulation. Running at 70 MIPS, the core executes PI or type-III compensators for both voltage and current loops within a single switching period. Two CAN modules additionally enable remote monitoring of supply health in server or telecom rectifiers.
推薦
Power Factor Correction (PFC)
In boost or bridgeless PFC front-ends, the DSPIC33EP128GS804-I/PT closes the input-current-shaping loop with deterministic latency: ADC conversions are triggered by the PWM time base and comparator events can ramp PWM duty in hardware, removing CPU-in-the-loop jitter. The 70 MIPS core supports average-current-mode control at switching frequencies typical of PFC stages. Dual flash partitions allow firmware updates of control coefficients in the field. PGA gain settings let one ADC front end span both line-voltage and current-shunt signals, reducing external analog components and board area.
推薦
DC-DC Converters (Digital Buck/Boost)
For point-of-load and intermediate-bus DC-DC stages, the DSPIC33EP128GS804-I/PT runs voltage-mode or current-mode loops using its high-speed PWM for sub-nanosecond-class duty adjustment via its fine-edge features and its ADC with PGA for low-noise current sensing across shunts. DMA moves sampled data between ADC and RAM without core intervention, keeping loop bandwidth deterministic. Comparators implement cycle-by-cycle overcurrent protection in hardware, independent of firmware, which is essential for reliability during load transients and short-circuit events in telecom and industrial 12 V/48 V distribution rails.
推薦
Solar Micro-Inverters
Microchip lists solar micro-inverters among the digital power-conversion applications supported by the GS family. The DSPIC33EP128GS804-I/PT simultaneously manages the panel-side MPPT loop and the grid-side inverter control using its multiple PWM modules with independent time bases. The ADC with PGA handles current transformers and voltage dividers across a wide dynamic range, while comparators provide hardware-level grid-fault shutdown. The CAN interface and general-purpose I/O support panel-level monitoring and communication in per-module architectures where a host controller aggregates telemetry.
推薦
Battery Chargers
Multi-stage battery charging (constant current, constant voltage, float) maps naturally onto the DSPIC33EP128GS804-I/PT's multi-loop PWM architecture: each stage is a separate control loop serviced by the same 70 MIPS core, with comparator-based overcurrent protection guarding each phase transition. The 128 KB flash holds charge algorithms, charge-parameter tables and logging; 8 KB RAM buffers telemetry. CAN support enables integration into battery-management networks for e-mobility chargers and industrial UPS batteries, while the industrial -40C to +85C rating covers outdoor charging enclosures.
推薦
Digital LED Drivers
High-power LED drivers benefit from the DSPIC33EP128GS804-I/PT's high-resolution PWM dimming and multi-channel output capability. Its PWM modules drive buck or boost LED stages with complementary outputs and programmable dead time, while the fast ADC monitors LED current through shunts with PGA gain for accuracy across dimming range. Hardware fault propagation forces safe PWM states on overcurrent, protecting expensive LED arrays. Dimming curves, thermal-derating tables and communication (CAN or UART) all fit comfortably in the 128 KB flash, making one controller sufficient for multi-string luminaires and stage lighting.
推薦
推薦產品摘要
工程參考資料，適用於 DSPIC33EP128GS804-I/PT — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | DSPIC33EP256GS804-I/PT | DSPIC33EP64GS804-I/PT | DSPIC33EP128GS704-I/PT | DSPIC33EP128GM304-I/PT |
|---|---|---|---|---|---|
| Package | 44-TQFP (10x10 mm) | 44-TQFP (10x10) - same | 44-TQFP (10x10) - same | 44-TQFP (10x10) - same | 44-TQFP (10x10) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| CPU Speed | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS |
| Flash Memory | 128 KB | 256 KB | 64 KB | 128 KB | 128 KB |
| Digital Power Peripherals (PGA, expanded PWM) | Yes (GS digital power family) | Yes | Yes | Reduced PWM channels | No (general-purpose GM family) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Digital-power-specific analog front end (對比DSPIC33EP128GM304-I/PT)
- Balanced 128 KB flash headroom (對比DSPIC33EP64GS804-I/PT)
- Cost-optimized path exists (對比DSPIC33EP128GS704-I/PT)
設計說明
Decouple every VDD pin (11, 21, 40) with a 100 nF ceramic capacitor placed within 2 mm of the pin, plus one bulk 4.7-10 uF per supply domain. Keep AVDD (pin 24) on its own filtered supply or an RC/LC filter from VDD, with AVSS (pin 25) returning to a quiet analog ground point - the ADC with PGA resolves millivolt signals from current shunts, so digital return currents must not share its ground path. Route PWM outputs (RE0-RE7, RD2-RD7) away from analog inputs AN0-AN13 to prevent switching spikes coupling into measurements.
The core runs at 70 MIPS from a single 3.3 V rail; core current scales with frequency, so budget several tens of milliamps plus I/O load current when sizing the 3.3 V regulator. For gate-drive-intensive designs, do not power MOSFET drivers from the same regulator as the DSC without local bulk capacitance - PWM switching transients on shared rails cause brownout resets. Enable the internal brownout reset and configure the watchdog timer in safety-critical power converters; the dual-partition flash lets you keep a validated fallback image for recovery.
Two frequent mistakes: (1) omitting the analog supply filtering on AVDD, which shows up as ADC noise in current-loop feedback and unstable compensator behavior; (2) assuming all GS80x pin functions are identical across variants - the GS704 has fewer PWM channels than the GS804, and GM-family parts change peripheral mapping, so pin-mux/Pinout code must be re-validated after any family substitution. Also verify the oscillator configuration: the 70 MIPS rate requires an external crystal or clock source configured via the PLL, and an incorrect PLL setting is a common first-bring-up failure.
合規資訊
Compliance data was not present in the verified web data. Microchip standard product is typically RoHS-compliant, but this must be confirmed from the official product page before export documentation.