EP2AGX95EF35C6 - Arria II GX FPGA 95K LE 1152-FBGA | Intel
MPN： EP2AGX95EF35C6 ✓ 啟用中EP2AGX95EF35C6 概覽
Arria II GX FPGAs sit within Intel's mid-range programmable logic portfolio, between the low-power Cyclone family and the high-performance Stratix family. The "GX" suffix denotes integrated multi-gigabit transceivers, making the family well-matched to applications that require high-speed serial I/O (e.g., PCIe Gen1/Gen2, Gigabit Ethernet, Serial RapidIO, CEI-6G, SDI, XAUI) without the cost of a full Stratix implementation. The Arria II architecture is built on a 40 nm TSMC process node, balancing logic capacity, transceiver performance, and power efficiency.
Key features of the EP2AGX95EF35C6 include 95K logic elements (LEs), 452 maximum user I/O pins, eight integrated transceivers operating up to 3.75 Gbps (some family members reach 6.375 Gbps), 4,478 Kbits of embedded RAM, 612 embedded 18x18 multipliers (DSP blocks), and a hard PCI Express Gen1/Gen2 controller IP block. The -6 speed grade indicates a moderately fast device within the Arria II GX speed bin hierarchy. The 1152-FBGA package supports high I/O and transceiver count, suitable for mid-to-high density designs.
The Arria II GX architecture uses logic elements (LEs) of 8-input look-up tables (LUTs), dedicated DSP blocks for arithmetic, MLAB blocks for distributed memory, and M9K/M144K memory blocks for larger storage. Transceivers include signal-conditioning features such as pre-emphasis, equalization, and output swing control, essential for compliance with high-speed serial standards. Configuration is supported through active serial, passive serial, fast passive parallel, and JTAG modes.
Typical applications include wireless baseband processing, video broadcast equipment (SDI/HD-SDI), industrial imaging and machine vision, test and measurement instrumentation, PCIe endpoint cards, and military/aerospace signal processing where moderate logic capacity is sufficient. The 1152-ball package and transceiver-rich I/O also suit custom ASIC prototyping.
When designing with EP2AGX95EF35C6, ensure power-rail sequencing meets the Arria II GX Power-On Reset (POR) requirements, since multiple voltage rails (VCC, VCCPT, VCCPGM, VCCA_GXB, VCC_GXB) must ramp in specified order. Use the Quartus II / Quartus Prime design suite for synthesis, place-and-route, and power analysis, and follow the PCB layout guidelines for flip-chip BGA and high-speed transceiver signal integrity.
This page synthesizes distributor pricing, drop-in same-package alternatives from Intel's Arria II GX family, and practical design notes that extend beyond the manufacturer datasheet.
直接替換替代品，適用於 EP2AGX95EF35C6 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EP2AGX95EF35C6 （相同外形與佔位） — 差異在於 Operating Temperature, Package, Speed Grade, PCIe Hard IP, Process Technology.
EP2AGX95EF35C6N
✅ 直接替換聯絡詢價
查看資料表 →EP2AGX95EF35C5G
✅ 直接替換聯絡詢價
查看資料表 →EP2AGX95EF35C4G
✅ 直接替換聯絡詢價
查看資料表 →EP2AGX95EF29C6G
✅ 直接替換聯絡詢價
查看資料表 →EP2AGX125EF35C6G
✅ 直接替換聯絡詢價
查看資料表 →EP2AGX95EF35C6 最大額定值與電氣特性
| Device Family | Arria II GX |
| Logic Elements (LEs) | 89,178 |
| Maximum User I/O Pins | 452 |
| Embedded Memory (Kbits) | 4,478 |
| Embedded 18x18 Multipliers | 612 |
| Number of Transceivers | 8 |
| Maximum Transceiver Data Rate | 3.75 Gbps |
| 封裝 | 1152-ball FCBGA |
| Speed Grade | -6 (mid) |
| Process Node | 40 nm |
| PCIe Hard IP | PCIe Gen1/Gen2 (x1/x4/x8) - per family datasheet |
| 工作溫度範圍 | Commercial (0C to 85C) per 'C' suffix |
| Configuration Modes | Active Serial, Passive Serial, Fast Passive Parallel, JTAG |
| 安裝類型 | Surface Mount (FCBGA) |
| RoHS 狀態 | Compliant |
EP2AGX95EF35C6 1152-ball fcbga 腳位配置指南
EP2AGX95EF35C6（1152-ball fcbga 封裝）的腳位配置。 此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。
無詳細腳位定義資料： EP2AGX95EF35C6.
請參閱 資料表 以查看完整腳位配置。
典型應用
EP2AGX95EF35C6 適用於 7 應用s: Wireless Baseband Processing, SDI / HD-SDI Video Broadcast Equipment, PCIe Endpoint Cards, Industrial Imaging and Machine Vision, Test and Measurement Instrumentation, Custom ASIC Prototyping, Aerospace and Defense Signal Processing.
Wireless Baseband Processing
The EP2AGX95EF35C6's 89,178 logic elements, 612 embedded 18x18 multipliers, and four 3.75 Gbps transceivers provide a balanced fabric for wireless baseband and remote-radio-unit (RRU) signal processing. The -6 speed grade achieves sufficient Fmax for LTE PHY rate-matching and channel coding, while 4,478 Kbits of embedded RAM holds soft-bit buffers and HARQ queues. The device is placed as the central DSP/control FPGA between RF front-end ADCs and the baseband ASIC, with CPRI/OBSAI serial links carried on the integrated transceivers. Compared with a pure ASIC, the FPGA enables late-binding to evolving 3GPP releases without re-spinning silicon.
推薦
SDI / HD-SDI Video Broadcast Equipment
The EP2AGX95EF35C6 targets broadcast video routers, format converters, and frame synchronizers with up to eight SDI/HD-SDI/3G-SDI links through its integrated transceivers. SMPTE 259M/292M/424M data rates fit comfortably within the 3.75 Gbps transceiver ceiling, while 95K LEs absorb color-space conversion, scaling, and overlay pipelines at full-HD raster. The 1152-FCBGA package supports the high I/O count needed for multi-channel parallel video buses plus JTAG and serial configuration. Designers use Quartus II/Prime with the Altera SDI MegaCore to instantiate multi-link receive and transmit paths.
推薦
PCIe Endpoint Cards
The Arria II GX hard PCIe Gen1/Gen2 controller IP block inside the EP2AGX95EF35C6 implements x1/x4/x8 endpoint functions without consuming soft logic, ideal for NIC, storage controller, and instrumentation cards. Eight transceivers cover PCIe lanes plus sideband serial interfaces, while 95K LEs provide endpoint application logic, DMA engines, and protocol translation. The 1152-FCBGA keeps PCB routing manageable with the F35 footprint. Power estimation in Quartus PowerPlay is recommended since PCIe PHY current scales with link width and traffic class.
推薦
Industrial Imaging and Machine Vision
With 8 transceivers supporting CoaXpress, Camera Link, or gigabit-Vision serial protocols and 95K LEs for image processing, the EP2AGX95EF35C6 fits high-speed line-scan and area-scan camera systems. 612 DSP blocks accelerate Sobel, FFT, and Bayer demosaic pipelines, while 4,478 Kbits of RAM buffers multiple frame lines on-chip. The commercial 0C to 85C operating range covers factory-floor enclosures; for outdoor installations, designers move to an industrial-grade variant such as EP2AGX95EF35I5N.
推薦
Test and Measurement Instrumentation
The EP2AGX95EF35C6's combination of 95K LEs, fast transceivers, and PCIe Gen2 hard IP makes it a flexible FPGA for arbitrary waveform generators, logic analyzers, and protocol analyzers. The -6 speed grade supports high sample-rate DSP signal processing, and the 1152-ball package exposes ample GPIO to front-end ADCs and DACs. JTAG, Active Serial, and Fast Passive Parallel configuration support field-upgradeable firmware, which is critical for calibration workflows. Power-supply design must accommodate the VCCA_GXB and VCC_GXB transceiver rails separately from VCCINT.
推薦
Custom ASIC Prototyping
ASIC design teams use the EP2AGX95EF35C6 as a mid-density prototyping vehicle for validating RTL, software stacks, and I/O behavior before mask tape-out. With 89K LEs and 4 Mbits of on-chip RAM, complex SoC subsystems can be partitioned across one or more FPGAs with high-speed serial links bridging chips. The 1152-FCBGA package supports split-PCB prototyping boards; the PCIe hard IP allows real-system integration testing. Quartus II/Prime provides ASIC-friendly synthesis and incremental compile, easing bring-up compared with vendor-locked tools.
推薦
Aerospace and Defense Signal Processing
Defense integrators use the EP2AGX95EF35C6 in ruggedized signal-processing subsystems for radar, electronic warfare, and secure communications, leveraging the device's ability to handle high-throughput DSP and serial I/O. The eight transceivers support custom serial fabrics, while 95K LEs and 612 DSP blocks deliver the arithmetic density required for FFT-based processing chains. The commercial speed/grade suits benign chassis environments; for harsher thermal ranges, migrate to the industrial EP2AGX95EF35I5N variant in the same package.
推薦
推薦產品摘要
工程參考資料，適用於 EP2AGX95EF35C6 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EP2AGX95EF35C6N | EP2AGX95EF35C5G | EP2AGX95EF35C4G | EP2AGX95EF29C6G | EP2AGX125EF35C6G |
|---|---|---|---|---|---|---|
| Package | 1152-ball FCBGA (F35) | 1152-ball FCBGA (F35) - same | 1152-ball FCBGA (F35) - same | 1152-ball FCBGA (F35) - same | 1152-ball FCBGA (F29) - same family, alt package code | 1152-ball FCBGA (F35) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 89,178 | 89,178 | 89,178 | 89,178 | 89,178 | 124,715 |
| Speed Grade | -6 | -6 | -5 | -4 | -6 | -6 |
| Embedded Memory (Kbits) | 4,478 | 4,478 | 4,478 | 4,478 | 4,478 | 8,294 |
| Transceivers | 8 up to 3.75 Gbps | 8 up to 3.75 Gbps | 8 up to 3.75 Gbps | 8 up to 3.75 Gbps | 8 up to 3.75 Gbps | 12 up to 3.75 Gbps |
| User I/O (max) | 452 | 452 | 452 | 452 | 452 | 452 |
| Operating Temperature | Commercial 0C to 85C | Commercial 0C to 85C | Commercial 0C to 85C | Commercial 0C to 85C | Commercial 0C to 85C | Commercial 0C to 85C |
| RoHS / Lead-Free (G suffix) | Compliant per datasheet | Pb-free (N suffix) | Pb-free (G suffix) | Pb-free (G suffix) | Pb-free (G suffix) | Pb-free (G suffix) |
主要差異化特點
- Highest-density 95K-LE Arria II GX device at the -6 speed grade (對比EP2AGX95EF35C5G)
- PCIe Gen2 x8 hard IP without consuming logic resources (對比EP2AGX125EF35C6G)
- 8 transceivers at 3.75 Gbps in a single 1152-ball package (對比EP2AGX45DF25C6G)
- Commercial temperature grade optimized for cost-sensitive designs (對比EP2AGX95EF35I5N)
設計說明
Arria II GX devices require multi-rail power sequencing per the family datasheet. VCCINT, VCCPD, VCCPT, VCCPGM, VCCA_GXB, and VCC_GXB must ramp in the order specified by the POR (Power-On Reset) section, or the device may latch up or fail to configure. Use a multi-rail controller (e.g., a TI TPS65086x or Lattice POWR607) to enforce monotonic ramps within 50 ms. Decouple each transceiver rail with 0.1 uF and 10 uF ceramics within 5 mm of the package balls. Estimated: total quiescent current for a fully-utilized EP2AGX95EF35C6 design is roughly 1-2 A from VCCINT plus 0.5-1.5 A from VCC_GXB, depending on transceiver utilization.
The 1152-ball FCBGA package has a junction-to-ambient thermal resistance (theta_JA) in the 12-15 C/W range with a standard 4-layer JEDEC PCB, depending on airflow. At maximum utilization (95K LEs at high toggle rate plus 8 active transceivers), die power may approach 10-15 W. A solid ground pad array with thermal vias under the package's central balls is essential for heat extraction; forced airflow is recommended above 8 W. Run Quartus PowerPlay early in the design cycle to refine the thermal budget for your specific logic utilization.
The 1152-FCBGA uses a 1.0 mm pitch (typical for Arria II GX F35 package). Route all differential transceiver pairs with 100 ohm differential impedance and length-matching within the tolerance specified by the protocol (e.g., 150 mil for PCIe, 5 mil for SDI). Keep reference planes unbroken under transceiver channels and avoid routing LVDS/TTL signals across the same layers. Use the Intel/Altera pin-out file and IBIS models for accurate SI simulation; the Quartus II Fitter also produces a board-level pin-out report.
Choose the configuration mode that matches your boot-time requirement: fast passive parallel (~100 ms) for fast boot, active serial (~200-500 ms) for low pin-count boot, JTAG for development. The EP2AGX95EF35C6 supports dual-boot images in some modes, allowing fallback to a known-good image if primary boot fails. Always strap MSEL pins correctly and pull CONF_DONE high via external 10 kohm to indicate successful configuration; leave nSTATUS open or pulled high per datasheet.
Transmitter pre-emphasis and receiver equalization must be tuned per channel using the Arria II GX Transceiver Toolkit, available in Quartus II/Prime. For SDI links, use the Altera SDI MegaCore with internal pattern generators to bring-up each channel before protocol-stack integration. Long PCB traces (>10 inches) typically require both pre-emphasis and CTLE tuning. Verify eye-mask compliance with an oscilloscope at the receiver end; rebuild PCB stack-up if eye margins are below 20%.
合規資訊
RoHS and lead-free status per Intel/Altera Arria II GX datasheet. AEC-Q100 not applicable (FPGA, not automotive-grade IC).
