HI5766KCBZ - 10-Bit 60MSPS CMOS ADC, 28-SOIC | Renesas
MPN： HI5766KCBZ ✗ 停產HI5766KCBZ 概覽
An ADC (analog-to-digital converter) is a semiconductor device that samples a continuous-time analog signal and quantizes each sample into a binary code at a defined sample rate. ADCs sit in the signal chain between an analog front-end (amplifiers, filters, muxes) and a digital processor (DSP, FPGA, microcontroller). High-speed pipelined ADCs such as the HI5766KCBZ deliver many bits per sample at rates from tens to hundreds of MSPS and are a sub-class of data converters under the broader power management / mixed-signal hierarchy.
Key differentiating features of the HI5766KCBZ include 10-bit resolution at 60 MSPS, low 260 mW power consumption for its speed class, CMOS output levels for direct interface to 3.3 V / 5 V logic, output data latches with 7-clock-cycle latency, and a fully differential pipelined core with internal sample-and-hold that simplifies analog front-end design. For internal voltage reference variants the datasheet points the reader to the HI5767 family.
Architecturally, the HI5766KCBZ uses a fully differential switched-capacitor pipeline that delivers one conversion per clock cycle after the initial pipeline latency, with output latches presenting valid data 7 clocks later. The internal sample-and-hold minimizes aperture uncertainty and front-end drive requirements, while CMOS outputs eliminate the need for external level shifters when interfacing to common ASICs and FPGAs at 3.3 V.
Typical applications for the HI5766KCBZ include professional video digitizers, medical imaging front-ends, set-top box and IF sampling chains, instrumentation and oscilloscope input stages, and communications receivers where moderate dynamic range at low power is required. It fits wherever a 10-bit, 60 MSPS CMOS ADC is the right speed/resolution trade-off.
A key design consideration is that the HI5766KCBZ is pin-for-pin compatible with the older HI5746 family, so engineers migrating legacy 10-bit designs can re-use existing PCB footprints; however, where an internal voltage reference is required, the HI5767 should be evaluated instead.
This page synthesizes current distributor inventory, drop-in compatible alternatives, and practical design notes for engineers evaluating the HI5766KCBZ for both new designs and legacy board reuse.
直接替換替代品，適用於 HI5766KCBZ — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： HI5766KCBZ （相同外形與佔位） — 差異在於 Package, Architecture, Resolution, Input Type, Data Interface.
HI5766KCAZ
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →HI5746KCBZ
✅ 直接替換聯絡詢價
查看資料表 →ADS901E/1KG4
✅ 直接替換聯絡詢價
查看資料表 →ADS7822PBG4
✅ 直接替換聯絡詢價
查看資料表 →ADS8505IDBRG4
✅ 直接替換聯絡詢價
查看資料表 →ADS8401IBPFBT
✅ 直接替換聯絡詢價
查看資料表 →HI5766KCBZ 最大額定值與電氣特性
| 解析度 | 10 bits |
| Sample Rate | 60 MSPS |
| Number of Inputs | 1 |
| Architecture | Pipelined, fully differential |
| Input Type | Differential, with internal sample-and-hold |
| 輸出類型 | CMOS, parallel |
| Output Data Latency | 7 clock cycles |
| Power Dissipation | 260 mW at 60 MSPS |
| 封裝 | 28-pin SOIC (wide-body) |
| Process Technology | CMOS |
| 安裝類型 | Surface Mount |
| Pin Compatibility | Pin-for-pin with HI5702, HI5703, HI5746 |
| Internal Voltage Reference | Not integrated - see HI5767 for internal reference variant |
HI5766KCBZ 腳位配置
| 腳位 1 | VD — Digital supply voltage |
| 腳位 2 | GND — Ground |
| 腳位 3 | OE — Output enable (active high) |
| 腳位 4 | D9 — Data output bit 9 (MSB) |
| 腳位 5 | D8 — Data output bit 8 |
| 腳位 6 | D7 — Data output bit 7 |
| 腳位 7 | D6 — Data output bit 6 |
| 腳位 8 | D5 — Data output bit 5 |
| 腳位 9 | D4 — Data output bit 4 |
| 腳位 10 | D3 — Data output bit 3 |
| 腳位 11 | D2 — Data output bit 2 |
| 腳位 12 | D1 — Data output bit 1 |
| 腳位 13 | D0 — Data output bit 0 (LSB) |
| 腳位 14 | GND — Ground |
| 腳位 15 | VA — Analog supply voltage |
| 腳位 16 | VREF — External voltage reference input |
| 腳位 17 | GND — Ground |
| 腳位 18 | AIN+ — Differential analog input positive |
| 腳位 19 | AIN- — Differential analog input negative |
| 腳位 20 | GND — Ground |
| 腳位 21 | CLK — Clock input |
| 腳位 22 | GND — Ground |
| 腳位 23 | NC — Not connected (per datasheet) |
| 腳位 24 | NC — Not connected (per datasheet) |
| 腳位 25 | NC — Not connected (per datasheet) |
| 腳位 26 | NC — Not connected (per datasheet) |
| 腳位 27 | NC — Not connected (per datasheet) |
| 腳位 28 | NC — Not connected (per datasheet) |
典型應用
HI5766KCBZ 適用於 6 應用s: Professional Video Digitizer Front-End, Medical Imaging Front-End (Ultrasound/Endoscope), IF Sampling for Communications Receivers, Test & Measurement Instrumentation, Set-Top Box / IF Sampling Demodulator, Industrial Process-Control Data Acquisition.
Professional Video Digitizer Front-End
The HI5766KCBZ is well suited to professional SD/HD video digitizer front-ends because its 60 MSPS sample rate comfortably exceeds the Nyquist requirement for 27 MHz component video and 74.25 MHz HD-SDI subcarrier harmonics. The 10-bit resolution matches the 10-bit processing pipeline commonly used in broadcast studio equipment and broadcast cameras. Fully differential pipelined architecture suppresses common-mode noise from long analog input traces, while CMOS outputs interface directly to FPGA deserializers without level shifters. Estimated: at 60 MSPS the ADC draws ~260 mW, so a small copper pour is sufficient thermal management in a 1U rack frame.
推薦
Medical Imaging Front-End (Ultrasound/Endoscope)
In medical imaging front-ends such as ultrasound receive-channel ADCs or endoscope video capture, the HI5766KCBZ delivers the 10-bit dynamic range and 60 MSPS throughput necessary to digitize filtered transducer or CCD outputs. The internal sample-and-hold minimizes aperture jitter, which directly impacts image signal-to-noise ratio in B-mode ultrasound. CMOS outputs pair naturally with low-power FPGA image processors, while the 260 mW dissipation eases thermal design in patient-contact enclosures. Estimated: a fully populated 8-channel receiver using one HI5766KCBZ per channel stays within ~2.1 W total ADC budget.
推薦
IF Sampling for Communications Receivers
For narrowband communications receivers and software-defined radio IF sampling, the HI5766KCBZ offers the 60 MSPS rate needed to directly sample 21.4 MHz or 70 MHz IF strips. The 10-bit resolution combined with the fully differential input provides adequate spurious-free dynamic range for adjacent-channel rejection in fixed-wireless links. Differential pipelined architecture rejects common-mode noise from digital baseband and clock traces. Designers can place the ADC close to the mixer and rely on the 7-clock deterministic latency when synchronizing demodulator DSP blocks downstream.
推薦
Test & Measurement Instrumentation
Digital oscilloscope input stages, transient recorders, and digitizer cards benefit from the HI5766KCBZ 60 MSPS rate and 10-bit resolution, which together cover most mid-bandwidth data acquisition needs up to ~25 MHz analog bandwidth. The internal sample-and-hold and pipelined architecture minimize front-end drive complexity, while CMOS outputs drive standard 3.3 V FPGAs without level translation. For lower-speed precision measurements the 10-bit quantizer is supplemented by averaging or oversampling inside the FPGA, where the 7-cycle latency is well-defined and easy to compensate for. Estimated: a benchtop 4-channel digitizer card using 4x HI5766KCBZ totals ~1.04 W ADC power.
推薦
Set-Top Box / IF Sampling Demodulator
In set-top box receivers and cable modem IF sampling chains, the HI5766KCBZ provides a low-power 60 MSPS path for digitizing 36 MHz or 44 MHz IF outputs from the tuner. The CMOS outputs lower BOM cost versus LVDS-interface ADCs and connect directly to consumer-grade SoCs. The 7-clock latency pairs well with deterministic demodulator loops requiring precisely-timed sample alignment. Estimated: a complete IF-sampling front-end card with one HI5766KCBZ, a 25 MHz SAW filter, and clock oscillator fits in a 1 square inch PCB area, enabling compact STB form factors.
推薦
Industrial Process-Control Data Acquisition
For industrial multi-channel data-acquisition modules requiring simultaneous sampling of vibration, acoustic emission, or motor-control feedback signals, the HI5766KCBZ provides the 60 MSPS throughput and 10-bit resolution for oversampled condition-monitoring streams. The fully differential pipelined core rejects the common-mode noise present in factory-floor environments with switching power stages. Pin-for-pin compatibility with HI5746 enables direct footprint reuse for legacy upgrade programs without PCB rework. Estimated: at 0.7 V analog input swing and 260 mW dissipation, junction temperature stays well below 100 degrees C with a 1 square inch copper pour.
推薦
推薦產品摘要
工程參考資料，適用於 HI5766KCBZ — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | HI5766KCAZ | HI5746KCBZ | ADS901E/1KG4 | ADS7822PBG4 | ADS8505IDBRG4 | ADS8401IBPFBT |
|---|---|---|---|---|---|---|---|
| Brand | Renesas / Intersil | Renesas / Intersil | Renesas / Intersil | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 28-SOIC (wide-body) | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same | 28-SOIC - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 12 bits | 16 bits | 16 bits |
| Sample Rate | 60 MSPS | 60 MSPS | 40 MSPS (typical, -33%) | 20 MSPS (-67%) | 200 kSPS (-99.7%) | 250 kSPS (-99.6%) | 1.25 MSPS (-98%) |
| Architecture | Pipelined, fully differential | Pipelined, fully differential | Pipelined, fully differential | Pipelined | SAR | SAR | SAR |
| Output Type | CMOS, parallel | CMOS, parallel | CMOS, parallel | CMOS, parallel | Serial/parallel | Parallel | Parallel |
| Pin-to-Pin with HI5746 | Yes | Yes | Yes (same part) | No | No | No | No |
主要差異化特點
- Pin-for-pin compatible with legacy HI5746 family (對比ADS901E/1KG4)
- 60 MSPS sample rate among 10-bit CMOS-output ADCs in legacy footprints (對比ADS901E/1KG4)
- Fully differential pipelined architecture with internal sample-and-hold (對比ADS7822PBG4)
- 260 mW low power for the speed class (對比ADS8505IDBRG4)
設計說明
Place input coupling capacitors as close as possible to pins 18 (AIN+) and 19 (AIN-) of the 28-SOIC package. Use a differential microstrip routing with 100 ohm characteristic impedance and matched trace lengths to within 0.5 mm to preserve common-mode rejection. Decouple VA (pin 15) and VD (pin 1) with separate 0.1 uF ceramic capacitors to a common low-impedance ground plane to avoid coupling digital noise into the analog supply.
Do not assume the HI5766KCBZ has an internal voltage reference - it requires an external reference on pin 16 (VREF). For internal-reference variants, evaluate the HI5767 family which shares the same 28-SOIC footprint. Also note the 7-clock pipeline latency: DSP code consuming HI5766KCBZ data must subtract 7 sample periods from the clock counter when aligning to the analog input edge.
Drive the CLK input (pin 21) with a low-jitter clock source; aperture uncertainty is directly set by the clock jitter, and at 60 MSPS a 5 ps RMS jitter limits SNR to ~57 dB for a 25 MHz analog input. Use an LVCMOS driver close to the CLK pin, and keep the clock trace short and isolated from the parallel CMOS outputs that switch on the same clock edge to avoid coupling back into the analog front-end.
At 60 MSPS the HI5766KCBZ dissipates approximately 260 mW (estimated from datasheet typical value). The 28-SOIC wide-body package requires minimal thermal management on a standard 1 oz 4-layer PCB with at least 0.5 square inches of ground-connected copper pour, keeping junction rise well under 30 C above ambient. Avoid placing the device adjacent to switching regulators; route analog supplies through LDO post-regulation if necessary.
合規資訊
RoHS and lead-free compliant per Renesas product page; AEC-Q100 not applicable for this non-automotive-grade ADC part.
