HI5746KCBZ - 10-Bit 40MSPS ADC, CMOS Out, SOIC-28 | Renesas
MPN： HI5746KCBZ ⚠ 最後購買機會HI5746KCBZ 概覽
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous analog voltage and produces a discrete multi-bit digital code proportional to the input amplitude. Pipelined ADCs such as the HI5746 use a cascade of low-resolution flash stages to achieve high sampling rates while preserving modest power and die size, falling under the broader hierarchy: ADC -> data converter -> data acquisition IC -> mixed-signal semiconductor.
Key features include 40 MSPS guaranteed sampling rate, 10-bit resolution with no missing codes, a fully differential pipelined architecture with internal sample-and-hold, and a 7-clock-cycle output latency. CMOS output levels simplify direct interface to FPGAs, ASICs, or microcontrollers without external level shifters. The wide-body SOIC-28 footprint eases hand-prototyping and inspection while preserving excellent high-frequency analog grounding.
The device architecture combines a wide-bandwidth differential input sample-and-hold with multi-bit-per-stage pipelined sub-ranging conversion and proprietary error-correction logic, achieving low integral and differential non-linearity. Internal reference and clock-duty-cycle stabilization circuits minimize design overhead, and the part is specified over the commercial and industrial temperature ranges.
Typical applications include CCD/CIS imaging digitizers, medical ultrasound front ends, professional video digitizing, set-top box video capture, digital oscilloscope front ends, and baseband I/Q sampling in communications receivers. Pin-for-pin compatibility with the HI5702/HI5703 families enables straightforward design reuse.
When designing with this ADC, provide low-impedance analog and digital ground planes that meet only at the AGND/DGND pins of the part. A 10 uF tantalum plus 0.1 uF ceramic bypass close to AVDC and a clean, low-jitter encode clock are essential to realize the datasheet SNR and SFDR performance.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical PCB-layout notes not gathered in a single place in the manufacturer datasheet, giving procurement and design engineers a single reference for the HI5746KCBZ.
直接替換替代品，適用於 HI5746KCBZ — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： HI5746KCBZ （相同外形與佔位） — 差異在於 Package, Input Type, Architecture, RoHS Status, Data Interface.
HI5746KCBZ-T
✅ 直接替換聯絡詢價
查看資料表 →HI5746KCB
✅ 直接替換聯絡詢價
查看資料表 →HI5767/4CBZ
✅ 直接替換聯絡詢價
查看資料表 →HI5767/4CBZ-T
✅ 直接替換聯絡詢價
查看資料表 →HI5746KCBZ 最大額定值與電氣特性
| 解析度 | 10 bit |
| 取樣率 | 40 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined (fully differential) |
| Input Type | Differential, with internal Sample-and-Hold |
| 輸出類型 | CMOS, parallel |
| Output Latency | 7 clock cycles |
| Analog Supply Voltage | +5 V (typ) |
| Digital Supply Voltage | +5 V (typ) or +3.3 V (interface) |
| Power Dissipation | 225 mW at 40 MSPS (typ) |
| 工作溫度範圍 | -40C to +85C (industrial, KCBZ suffix) |
| 封裝 | 28-pin SOIC Wide (300 mil) |
| 安裝類型 | Surface Mount |
| MSL 等級 | 1 (unlimited floor life) |
| Lead-Free / RoHS | Yes (RoHS compliant) |
| Pin Compatibility | Pin-for-pin with HI5702 / HI5703 family |
| Lifecycle Note | Support limited to existing adopters; last-time-buy posture |
HI5746KCBZ 腳位配置
| 腳位 1 | AVDD — Analog +5V supply |
| 腳位 2 | AVDD — Analog +5V supply |
| 腳位 3 | AGND — Analog ground |
| 腳位 4 | AIN+ — Differential analog input, non-inverting |
| 腳位 5 | AIN- — Differential analog input, inverting |
| 腳位 6 | AGND — Analog ground |
| 腳位 7 | VREF — Internal reference decoupling |
| 腳位 8 | AGND — Analog ground |
| 腳位 9 | REFT — Internal top reference decoupling |
| 腳位 10 | REFB — Internal bottom reference decoupling |
| 腳位 11 | AGND — Analog ground |
| 腳位 12 | CLK — Encode clock input |
| 腳位 13 | CLKB — Complementary encode clock (optional) |
| 腳位 14 | DRVDD — Digital output driver supply |
| 腳位 15 | DRGND — Digital output driver ground |
| 腳位 16 | DB9 — Data output bit 9 (MSB) |
| 腳位 17 | DB8 — Data output bit 8 |
| 腳位 18 | DB7 — Data output bit 7 |
| 腳位 19 | DB6 — Data output bit 6 |
| 腳位 20 | DB5 — Data output bit 5 |
| 腳位 21 | DB4 — Data output bit 4 |
| 腳位 22 | DB3 — Data output bit 3 |
| 腳位 23 | DB2 — Data output bit 2 |
| 腳位 24 | DB1 — Data output bit 1 |
| 腳位 25 | DB0 — Data output bit 0 (LSB) |
| 腳位 26 | DRGND — Digital output driver ground |
| 腳位 27 | OE — Output enable (active high) |
| 腳位 28 | DRVDD — Digital output driver supply |
典型應用
HI5746KCBZ 適用於 6 應用s: CCD / CIS Image Digitizer, Medical Ultrasound Receive Channel, Professional Video Capture Card, Digital Oscilloscope Front End, Baseband I/Q Sampler, Set-Top Box Video Decoder.
CCD / CIS Image Digitizer
The HI5746KCBZ suits CCD and CIS imaging front ends because its 40 MSPS sampling rate supports VGA-class video digitizing at 30 fps with headroom. The fully differential 10-bit pipeline captures the full pixel-recovery transient while preserving the signal-to-noise ratio required for downstream color interpolation. The 28-pin SOIC wide footprint keeps analog and digital grounds segregated, which is critical at 40 MSPS edge rates to avoid digital feedback into the analog front end.
推薦
Medical Ultrasound Receive Channel
The HI5746KCBZ fits ultrasound receiver signal chains because 10-bit resolution at 40 MSPS captures return-echo envelopes after time-gain compensation, and the differential pipelined core rejects common-mode pickup from piezoelectric transducers. CMOS output levels drive the beamforming FPGA directly without level shifters, lowering BOM cost in dense multi-channel systems. Designers should pair this ADC with low-noise LNA and VGA front ends such as the AD8332 to preserve diagnostic image SNR.
推薦
Professional Video Capture Card
Studio-grade video capture cards benefit from the HI5746KCBZ's 40 MSPS capability, which oversamples standard-definition and component-video streams at integer ratios, easing downstream digital filtering. The CMOS output bus interfaces natively to FPGAs and ASSPs without external bus transceivers, reducing both part count and board complexity. Its pin-for-pin compatibility with the legacy HI5702 / HI5703 family simplifies board reuse when migrating existing capture designs.
推薦
Digital Oscilloscope Front End
The HI5746KCBZ serves digital-storage oscilloscope input stages where single-shot bandwidth above 10 MHz and a 7-clock-cycle latency are needed for accurate trigger placement. The CMOS output bus feeds downstream FPGA capture memory at full bus width without buffering, and the wide SOIC-28 package accommodates the analog/digital ground partitioning required at 40 MSPS. Lower encode rates down to DC let a single ADC serve multiple time-base ranges, simplifying front-end multiplexing.
推薦
Baseband I/Q Sampler
Software-defined-radio receivers use the HI5746KCBZ to digitize baseband I and Q channels simultaneously with two ADCs sharing the same encode clock, preserving quadrature balance. The fully differential pipelined architecture rejects LO leakage and common-mode spurs, and CMOS output levels stream directly to the DSP or FPGA for demodulation. Pairing with a fast op-amp such as the AD8001 maintains the noise figure demanded by narrow-band demodulation.
推薦
Set-Top Box Video Decoder
Set-top boxes use the HI5746KCBZ to digitize composite or component analog video at 27 MSPS for NTSC/PAL or 40 MSPS for higher-bandwidth signals. The internal sample-and-hold and pipelined architecture ensure no missing codes across the full input range, eliminating visible macroblocking during fast scene transitions. The wide SOIC-28 footprint fits conventional consumer-electronics PCB cost targets while still supporting the analog grounding discipline required at 40 MSPS.
推薦
推薦產品摘要
工程參考資料，適用於 HI5746KCBZ — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | HI5746KCBZ-T | HI5746KCB | HI5767/4CBZ | HI5767/4CBZ-T | ADS8401IBPFBR |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Package | 28-pin SOIC Wide | 28-pin SOIC Wide - same | 28-pin SOIC Wide - same | 28-pin SOIC Wide - same | 28-pin SOIC Wide - same | 48-pin TQFP - different footprint |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 12 bit |
| Sampling Rate | 40 MSPS | 40 MSPS | 40 MSPS | Higher than 40 MSPS | Higher than 40 MSPS | 40 MSPS |
| Output Type | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel |
| Internal Reference | No (external recommended) | No (external recommended) | No (external recommended) | Yes (internal) | Yes (internal) | Yes (internal) |
| Lifecycle Status | Last-time-buy (Renesas) | Last-time-buy | Last-time-buy | Active successor | Active successor | Active (TI) |
| Pin Compatibility | Reference part | Identical die, same SOIC-28 wide footprint | Pin-for-pin (industrial temp variant) | Pin-for-pin 'complete replace' per FindIC | Pin-for-pin 'complete replace' per FindIC | Not pin-compatible (TQFP-48) |
主要差異化特點
- Pin-for-pin functionally compatible with the legacy HI5702 / HI5703 family (對比HI5746KCBZ-T (tape-and-reel variant))
- Compact 28-pin SOIC wide-body package with separated analog/digital grounds (對比ADS8401IBPFBR (48-pin TQFP, TI))
- 7-clock-cycle deterministic output latency (對比ADS8401IBPFBR (5-clock latency, TI))
- Fully differential pipelined architecture with internal sample-and-hold (對比HI5767/4CBZ (successor with internal reference))
設計說明
Use a four-layer board with a continuous, unbroken ground plane directly beneath the SOIC-28 footprint. The analog and digital grounds on the HI5746KCBZ are pinned out separately; tie them together only at the IC's AGND pins to avoid digital return currents polluting the analog front end. Place the 10 uF tantalum plus 0.1 uF ceramic AVCC bypass within 3 mm of the AVDD pins. Recommended severity: critical.
Drive the CLK pin with a low-jitter 50 percent duty-cycle encode clock from a dedicated oscillator or FPGA PLL output; clock jitter directly degrades SNR by approximately 20*log10(2*pi*fin*sigma_t). Keep the CLK trace short, 50-ohm controlled-impedance, and routed away from the analog input pair. A complementary CLKB input is provided for differential clocking when system EMI is a concern. Recommended severity: critical.
The HI5746KCBZ draws about 225 mW at 40 MSPS from a +5 V analog rail; isolate that rail from the digital +5 V supply with an LC pi-filter or ferrite bead to prevent switching noise coupling into the reference. Add 0.1 uF X7R ceramics at every DRVDD pin and a bulk 10 uF tantalum near the digital cluster. Decoupling is the single biggest determinant of SFDR in a real board. Recommended severity: recommended.
Do not leave the OE pin floating; it must be tied either to DRVDD (outputs always enabled) or driven by the FPGA's frame-gate logic to keep bus contention off the digital rail during power-up. Avoid placing external logic buffers directly between the HI5746KCBZ outputs and the FPGA inputs - the CMOS bus can drive short traces directly, and adding buffers injects timing skew. Recommended severity: recommended.
Route the 10-bit CMOS output bus as a tightly matched-length group (skew less than 1 ns across all DB[9:0] lines) so the receiving FPGA captures the bus with a single clock edge. Place the output driver supply (DRVDD) and its ground (DRGND) pins on opposite sides of the bus pinout so return currents flow under the signal lines. Maintain at least 3x trace spacing between analog input traces and digital output bus. Recommended severity: recommended.
合規資訊
RoHS-compliant per Renesas HI5746 product page. Industrial temperature grade (-40C to +85C) per KCBZ ordering suffix. MSL 1 floor-life rated. Halogen-free status not explicitly stated in retrieved data; treat as unknown.
