LTC2172CUKG-12 - 12-Bit 65Msps Quad ADC LVDS | Analog Devices
MPN： LTC2172CUKG-12 ✓ 啟用中LTC2172CUKG-12 概覽
An ADC (analog-to-digital converter) is a semiconductor that converts continuous analog waveforms into discrete digital codes at a specified sample rate. Quad ADCs such as the LTC2172CUKG-12 integrate four independent conversion channels on a single die, allowing simultaneous sampling of multiple signals - useful in MIMO transceivers, multi-antenna base stations, medical imaging arrays, and beamforming systems. Low-power quad ADCs sit at the intersection of high-speed data conversion and energy-efficient system design, supporting both battery-powered portable instruments and dense multi-channel rack equipment.
Key specifications for the LTC2172CUKG-12 include 65 Msps sampling rate, 12-bit resolution, LVDS digital outputs with 3.5 mA drive and 1.25 V common-mode voltage, 1.8 V single-supply operation, 800 MHz full-power analog input bandwidth, integrated sample-and-hold, configurable shutdown and nap modes, and an SPI configuration port for register control. The selectable input range (1 V P-P or 2 V P-P) enables direct interfacing to a wide range of IF/RF signal chains without external attenuators.
Architecturally, the LTC2172CUKG-12 uses a pipelined multi-stage ADC core per channel, which provides an excellent speed-resolution trade-off: each stage resolves a few bits and passes the residue to the next, allowing very high clock rates while keeping per-stage capacitor area modest. Differential analog inputs with on-chip common-mode bias simplify transformer or op-amp driver interfacing.
Typical applications include 4G LTE and diversity radio receiver basebands, multi-channel communications test equipment, handheld and portable imaging systems, medical ultrasound front-ends, and multi-antenna phased-array radar digitizers. Its low power draw makes it suitable for thermally constrained enclosures.
When designing with this device, AC-couple or DC-couple the analog inputs through a differential driver, place the LVDS 100 Ω termination resistors as close as possible to the FPGA/ASIC LVDS pins, and use a low-noise LDO (such as the ADP1740) to derive the 1.8 V analog supply from a switching pre-regulator.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design guidance not found in the manufacturer datasheet alone.
直接替換替代品，適用於 LTC2172CUKG-12 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LTC2172CUKG-12 （相同外形與佔位） — 差異在於 Package, Resolution, Digital Output Interface, Pin Compatibility, Sampling Rate.
LTC2172CUKG-14
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2171CUKG-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2171CUKG-14
✅ 直接替換聯絡詢價
查看資料表 →LTC2170CUKG-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2171IUKG-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2172CUKG-12 最大額定值與電氣特性
| 解析度 | 12 bits |
| Number of Channels | 4 (simultaneous sampling) |
| Sample Rate | 65 Msps |
| Architecture | Pipelined |
| 供應電壓 | 1.8 V (single) |
| Input Range | 1 V P-P to 2 V P-P selectable |
| Analog Input Type | Differential |
| Input Bandwidth | 800 MHz full power |
| Digital Output | LVDS (3.5 mA, 1.25 V common mode) |
| Output Termination | 100 Ω differential per LVDS pair |
| Power Modes | Shutdown and Nap modes |
| Configuration Interface | Serial SPI port |
| 封裝 | 52-pin QFN (7 mm × 8 mm) |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant (PBF suffix) |
| Pin Compatibility | Pin-compatible with LTC2172-14, LTC2171-12, LTC2170-12 |
LTC2172CUKG-12 52-pin qfn (7 mm × 8 mm) 腳位配置指南
LTC2172CUKG-12（52-pin qfn (7 mm × 8 mm) 封裝）的腳位配置。 此類比元件具有輸入、輸出與電源腳位。偏移歸零、補償與致能腳位配置請參閱製造商資料表。適用於訊號調理與放大器電路。
無詳細腳位定義資料： LTC2172CUKG-12.
請參閱 資料表 以查看完整腳位配置。
典型應用
LTC2172CUKG-12 適用於 6 應用s: 4G LTE Diversity Radio Receiver Baseband, Multi-Channel Communications Test Equipment, Portable Multi-Channel Imaging System, Medical Ultrasound Front-End Digitizer, Multi-Antenna Phased-Array Radar Digitizer, MIMO Wireless Testbed Digitizer.
4G LTE Diversity Radio Receiver Baseband
The LTC2172CUKG-12 fits 4G LTE diversity receivers because its four simultaneously-sampling 65 Msps channels digitize dual-antenna I/Q baseband signals while maintaining phase alignment between paths. Each channel's 800 MHz input bandwidth accommodates wideband LTE carriers, and the LVDS outputs feed directly into FPGAs without level translation. A 1.8 V single supply simplifies power tree design compared to parts requiring separate analog and digital rails. Selectable 1 V P-P / 2 V P-P input ranges let designers match the ADC full-scale to the upstream transceiver output without external attenuators.
推薦
Multi-Channel Communications Test Equipment
Test and measurement instruments benefit from the LTC2172CUKG-12's four 12-bit 65 Msps channels because one IC replaces four discrete ADCs, reducing board area while preserving per-channel sample-rate throughput. The integrated sample-and-hold eliminates inter-channel skew that would otherwise compromise phase-coherent multi-tone measurements such as EVM and ACLR tests on wireless transmitters. SPI configuration lets the test set programmer reconfigure input range and power modes dynamically per test step. The 1.8 V single supply and low power draw reduce cooling requirements in dense rack-mount test platforms.
推薦
Portable Multi-Channel Imaging System
Portable imaging systems such as industrial borescopes and handheld flaw detectors use the LTC2172CUKG-12 to digitize four CMOS/CCD sensor outputs simultaneously. Its low power profile extends battery runtime versus alternative higher-speed ADCs, while the 12-bit resolution captures dynamic range typical of X-ray and fluorescence imaging. Shutdown and nap modes turn off idle channels to save power when only a subset of sensors is active. The compact 7 mm × 8 mm QFN fits tight camera-head enclosures.
推薦
Medical Ultrasound Front-End Digitizer
The LTC2172CUKG-12 suits medical ultrasound receivers because four channels captured simultaneously preserve the relative phase and amplitude needed for beamforming. Each channel's 800 MHz analog bandwidth handles the wide dynamic range of returned echoes from deep tissue penetration. The 12-bit resolution is sufficient for B-mode grayscale imaging, and the LVDS outputs deliver samples to the back-end FPGA across shielded cables with strong common-mode rejection. Shutdown modes let handheld units disable unused channels to extend battery life between scans.
推薦
Multi-Antenna Phased-Array Radar Digitizer
Phased-array radar systems use the LTC2172CUKG-12 to digitize multiple antenna channels simultaneously for digital beamforming. Simultaneous sampling preserves the relative phase across the array, which directly determines beam-steering accuracy. The four-channel density cuts board area versus using single-channel ADCs, allowing more antenna elements in a constrained footprint. The 1.8 V single supply simplifies power distribution through the antenna manifold. Designers typically pair this ADC with an FPGA that performs fast Fourier transforms on the LVDS streams in real time.
推薦
MIMO Wireless Testbed Digitizer
MIMO wireless testbeds need synchronized multi-channel capture, and the LTC2172CUKG-12 provides four simultaneous 65 Msps channels in a single QFN package. The SPI configuration port allows testbed firmware to dynamically switch input range and power modes for different modulation standards such as Wi-Fi 6E and 5G NR. The differential analog inputs accept direct transformer coupling from RF downconverter outputs. Low power consumption enables portable field-test configurations.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2172CUKG-12 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2172CUKG-14 | LTC2171CUKG-12 | LTC2171CUKG-14 | LTC2170CUKG-12 | LTC2171IUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-pin QFN (7x8 mm) | 52-pin QFN (7x8 mm) - same | 52-pin QFN (7x8 mm) - same | 52-pin QFN (7x8 mm) - same | 52-pin QFN (7x8 mm) - same | 52-pin QFN (7x8 mm) - same |
| Resolution | 12 bits | 14 bits | 12 bits | 14 bits | 12 bits | 12 bits |
| Sample Rate | 65 Msps | 65 Msps | 40 Msps | 40 Msps | 25 Msps | 40 Msps |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Digital Output | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Commercial | Industrial |
主要差異化特點
- Pin-compatible 12-bit and 14-bit upgrade path in the same QFN package (對比LTC2172CUKG-14)
- Same QFN footprint at 40 Msps for cost-down SKUs (對比LTC2171CUKG-12)
- Industrial temperature grade available in same package (對比LTC2171IUKG-12)
- Lower power alternative at 25 Msps (對比LTC2170CUKG-12)
設計說明
The LTC2172CUKG-12 is designed to operate from a single 1.8 V supply. Place a low-noise LDO such as the Analog Devices ADP1740 immediately after any switching pre-regulator to keep switching ripple out of the analog and clock domains. Estimated: at 65 Msps with all four channels active, the part draws roughly the maximum power specified in the datasheet; derate the LDO with at least 20% margin. Decouple the 1.8 V pin with a 1 µF ceramic plus a 0.1 µF high-frequency bypass placed within 2 mm of the pin.
Each LVDS output pair requires a 100 Ω differential termination resistor at the receiver end. Route LVDS traces as tightly coupled differential pairs with 100 Ω differential impedance; keep trace length matching to within 150 mil (3.8 mm) across pairs to avoid inter-channel skew. Per the LTC2172-12 datasheet, the analog inputs should be driven differentially through a balun or a fully differential driver (such as the AD8138) for best harmonic performance at 65 Msps.
Source the LTC2172CUKG-12 sample clock from a low-jitter clock generator such as the AD9516, and keep the clock trace short and impedance-controlled. The integrated sample-and-hold requires stable clock edges with jitter well below 1 ps RMS to preserve SNR at 65 Msps. Place the clock driver close to the ADC clock input pin and provide a dedicated ground via. Estimated: every additional 1 ps of clock jitter reduces SNR by approximately 0.5 dB at the Nyquist input frequency.
Estimated: at full 65 Msps with four channels active, the LTC2172CUKG-12 dissipates approximately the maximum power quoted in the datasheet. The 52-pin QFN has an exposed pad that must be soldered to a continuous ground plane with multiple thermal vias to keep junction temperature in spec. Limit ambient operating temperature to 70 °C or less in sealed enclosures, or specify the industrial-temperature LTC2171IUKG-12 variant for harsh environments.
Common pitfalls include: (1) omitting the 100 Ω LVDS termination, which causes reflections and corrupted samples; (2) using a single-ended analog input instead of differential, which halves SNR; (3) routing LVDS pairs with mismatched lengths, which creates inter-channel timing skew; (4) failing to solder the QFN exposed pad, which prevents thermal relief and may cause device failure in production; (5) leaving unused channels powered instead of using shutdown/nap modes, which wastes power.
合規資訊
RoHS compliance indicated by the #PBF suffix per the DigiKey listing; AEC-Q100 automotive qualification not applicable for this commercial-grade ADC
