LTC2175IUKG-12 - 12-Bit 125Msps Quad ADC, Serial LVDS | ADI
MPN： LTC2175IUKG-12 ✓ 啟用中LTC2175IUKG-12 概覽
An ADC is a mixed-signal integrated circuit that converts continuous analog waveforms into discrete digital codes; pipelined ADCs specifically use a multi-stage switched-capacitor architecture to balance high sampling speed against moderate die area and power dissipation. The LTC2175 family sits inside the converter hierarchy as: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. It therefore serves wherever simultaneous multi-channel wide-bandwidth capture is needed, including communications baseband, radar, and instrumentation front ends.
Key features include ±0.3 LSB INL (typical) and ±0.1 LSB DNL (typical) with no missing codes over the full operating temperature range, plus a low 0.3 LSB RMS transition noise. The 52-pin QFN package provides a compact 7x8 mm footprint with an exposed pad (EP) that bonds the die substrate to PCB copper, lowering thermal resistance and improving high-temperature performance. Configuration is via SPI or a parallel mode-select interface, allowing trade-offs between sample rate, channel count, and output width.
Typical applications include diversity RF receivers, MIMO/Multi-IF downconverters, advanced wireless base stations, broadband wireless local loops, and portable test instrumentation. The quad-channel, simultaneous-sampling architecture is particularly well-suited to I/Q capture paths where phase coherence between channels is critical.
When designing in this device, allocate adequate ground returns and a solid ground pour on layer 2 beneath the QFN, and follow the analog input network shown in the datasheet (typically a small series damping resistor plus shunt capacitance) to control charge kickback at high input frequencies. Decouple AVDD and DVDD separately with low-ESR ceramics near the pins.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving the design engineer a single, decision-ready reference.
直接替換替代品，適用於 LTC2175IUKG-12 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LTC2175IUKG-12 （相同外形與佔位） — 差異在於 Package, Number of Channels, Resolution, Input Type, RoHS Status.
LTC2174IUKG-12
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2173IUKG-12
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2175IUKG-14
✅ 直接替換📋 參考替代品（不在目錄中）
LTC2175CUKG-14
✅ 直接替換聯絡詢價
查看資料表 →LTC2171IUKG-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2172IUKG-12
✅ 直接替換聯絡詢價
查看資料表 →LTC2175IUKG-12 最大額定值與電氣特性
| Manufacturer | Analog Devices (formerly Linear Technology) |
| Part Number | LTC2175IUKG-12 |
| 解析度 | 12 bits |
| Number of Channels | 4 (simultaneous sampling) |
| 取樣率 | 125 Msps max |
| Architecture | Pipelined |
| INL (typical) | ±0.3 LSB |
| DNL (typical) | ±0.1 LSB |
| Missing Codes | None (over temperature) |
| Transition Noise | 0.3 LSB RMS |
| Digital Output Format | Serial LVDS (2-lane / 1-lane) |
| Input Type | Single-ended/differential analog |
| 封裝 | 52-QFN (7x8 mm) with exposed pad |
| 安裝類型 | Surface Mount |
| Temperature Grade | Industrial |
| 工作溫度範圍 | -40C to +85C |
| Configuration Interface | SPI / parallel |
| RoHS | Compliant (Pb-free #PBF suffix) |
LTC2175IUKG-12 腳位配置
| 腳位 1 | SENSE — Analog input common-mode sense |
| 腳位 2 | GND — Analog ground |
| 腳位 3 | VDD — Analog supply (1.8 V typical) |
| 腳位 4 | REFN — Negative reference decoupling |
| 腳位 5 | REFP — Positive reference decoupling |
| 腳位 6 | VREF — Reference output |
| 腳位 7 | GND — Analog ground |
| 腳位 8 | INA+ — Channel A positive analog input |
| 腳位 9 | INA- — Channel A negative analog input |
| 腳位 10 | INB+ — Channel B positive analog input |
| 腳位 11 | INB- — Channel B negative analog input |
| 腳位 12 | GND — Analog ground |
| 腳位 13 | INC+ — Channel C positive analog input |
| 腳位 14 | INC- — Channel C negative analog input |
| 腳位 15 | IND+ — Channel D positive analog input |
| 腳位 16 | IND- — Channel D negative analog input |
| 腳位 17 | GND — Analog ground |
| 腳位 18 | ENC+ — Encode input positive |
| 腳位 19 | ENC- — Encode input negative |
| 腳位 20 | GND — Clock ground |
| 腳位 21 | OVDD — Output supply |
| 腳位 22 | GND — Digital ground |
| 腳位 23 | CS — SPI chip select |
| 腳位 24 | SCK — SPI serial clock |
| 腳位 25 | SDI — SPI serial data input |
| 腳位 26 | SDO — SPI serial data output |
| 腳位 27 | GND — Digital ground |
| 腳位 28 | OUTA+ — LVDS data output channel A positive |
| 腳位 29 | OUTA- — LVDS data output channel A negative |
| 腳位 30 | OUTB+ — LVDS data output channel B positive |
| 腳位 31 | OUTB- — LVDS data output channel B negative |
| 腳位 32 | OUTC+ — LVDS data output channel C positive |
| 腳位 33 | OUTC- — LVDS data output channel C negative |
| 腳位 34 | OUTD+ — LVDS data output channel D positive |
| 腳位 35 | OUTD- — LVDS data output channel D negative |
| 腳位 36 | GND — Digital ground |
| 腳位 37 | MODE — Mode / lane selection |
| 腳位 38 | OGND — LVDS output ground |
| 腳位 39 | OVDD — Output supply |
| 腳位 40 | CLKOUT+ — Clock output positive |
| 腳位 41 | CLKOUT- — Clock output negative |
| 腳位 42 | FR+ — Frame output positive |
| 腳位 43 | FR- — Frame output negative |
| 腳位 44 | OGND — LVDS ground |
| 腳位 45 | OVDD — Output supply |
| 腳位 46 | DNC — Do not connect |
| 腳位 47 | DNC — Do not connect |
| 腳位 48 | GND — Analog ground |
| 腳位 49 | OVDD — Output supply |
| 腳位 50 | DNC — Do not connect |
| 腳位 51 | DNC — Do not connect |
| 腳位 52 | GND — Analog ground |
典型應用
LTC2175IUKG-12 適用於 7 應用s: Diversity RF Receivers, MIMO / Multi-IF Downconverters, Wireless Base Station Receiver Cards, Broadband Wireless Local Loop, Portable Test Instrumentation, Radar and Lidar Digitiser Subsystems, Medical Imaging Receivers.
Diversity RF Receivers
The LTC2175IUKG-12's four simultaneous-sampling channels digitise the I/Q streams from two or more antenna branches at 125 Msps, preserving phase coherence required for diversity combining. The serial LVDS interface minimises board area while the 0.3 LSB RMS transition noise keeps SNR high in narrowband cellular links. Pin-compatible drop-in: LTC2174IUKG-12 (105 Msps) for cost-down when 125 Msps headroom is not required.
推薦
MIMO / Multi-IF Downconverters
Each of the four input channels can be fed from a separate IF chain after mixing, allowing a single LTC2175IUKG-12 to capture multiple intermediate frequencies in parallel at full 125 Msps. The pipelined architecture delivers ±0.3 LSB INL across temperature for clean demodulation of multi-carrier waveforms in 4G/5G base stations.
推薦
Wireless Base Station Receiver Cards
Baseband receivers for LTE and 5G front-end cards require wideband simultaneous capture of multiple antenna streams; the LTC2175IUKG-12 provides 4 channels @ 125 Msps with no missing codes, sustaining digital pre-distortion loops and beam-forming DSP. The 52-QFN exposed pad couples die heat to inner-layer copper, suitable for chassis-mounted boards.
推薦
Broadband Wireless Local Loop
Fixed-wireless and last-mile access points need four channels of synchronised 80-125 Msps conversion. The LTC2175IUKG-12's low 0.3 LSB RMS transition noise preserves digital modulation error vector magnitude (EVM) over OFDM waveforms with hundreds of carriers.
推薦
Portable Test Instrumentation
Battery-powered oscilloscopes, spectrum-analyser intermediate-IF cards, and signal-intelligence recorders benefit from the LTC2175IUKG-12's quad synchronous capture and serial LVDS outputs that isolate the digital switching noise from sensitive analog rails. Industrial -40C to +85C rating covers field-deployed instrument enclosures without additional thermal screening.
推薦
Radar and Lidar Digitiser Subsystems
Phase-coherent radar I/Q and pulsed lidar front-end boards use multi-channel synchronised ADCs; the LTC2175IUKG-12 returns four parallel samples at 125 Msps with sub-LSB noise, ideal for staring-array lidar aggregation and FMCW chirp capture. Its -40C to +85C rating suits outdoor and airborne enclosures without downgrading to military temperature grades.
推薦
Medical Imaging Receivers
Ultrasound beamformer front-end receivers digitise 4-32 channels at 40-125 Msps. With 4 channels per IC, a single LTC2175IUKG-12 services a sub-array, providing ±0.3 LSB INL linearity and 0.3 LSB RMS noise critical for low-amplitude echo capture. Its industrial temperature grade suits cart-based clinical equipment.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2175IUKG-12 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2174IUKG-12 | LTC2173IUKG-12 | LTC2175IUKG-14 | LTC2171IUKG-12 | LTC2172IUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (7x8) | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 14 bit | 12 bit | 12 bit |
| Sampling Rate | 125 Msps | 105 Msps | 80 Msps | 125 Msps | 65 Msps | 105 Msps |
| Channels | 4 (simultaneous) | 4 (simultaneous) | 4 (simultaneous) | 4 (simultaneous) | 4 (simultaneous) | 4 (simultaneous) |
| INL (typ) | ±0.3 LSB | ±0.3 LSB | ±0.3 LSB | ±0.5 LSB | ±0.3 LSB | ±0.3 LSB |
| Output Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
| Temperature Range | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Highest sample rate in the 12-bit LTC217x QFN-52 family (對比LTC2173IUKG-12)
- Quad-channel simultaneous sampling on a single ADC (對比AD9268XCPZ-125)
- Industrial temperature grade drop-in alternative path (對比LTC2175CUKG-14)
- Same package offers 14-bit upgrade path (對比LTC2175IUKG-14)
設計說明
Reference the analog input network shown in the datasheet typically a 25 ohm series damping resistor followed by a few pF shunt capacitance right at the package pin. Inadequate damping at 125 Msps will allow the pipeline's charge-kickback transient to introduce integral non-linearity. Use a wide ground pour on layer 2 directly under the 52-QFN exposed pad to dissipate heat to the chassis or inner copper.
Decouple AVDD with a 1.0 uF X7R 0603 ceramic plus a 100 nF X7R 0402 in parallel, each within 2 mm of the pin. DVDD (or OVDD) for the LVDS I/O requires a separate ferrite bead plus 100 nF capacitor to suppress digital switching noise from leaking back into the analog rails. The datasheet recommends a 100 nF cap on REFP and a 1.0 uF on REFN to set the internal reference network.
Differential encode clock routing is mandatory; driving ENC with a single-ended TTL signal degrades sample-to-sample jitter from ~70 fs to >1 ps, destroying dynamic range. Keep ENC+/ENC- as a 100 ohm differential pair, length-matched to within 0.5 mm, and route away from analog input traces. Verify pin 1 orientation against the printed dot before PCB assembly; the QFN-52 has no obvious top-side identifier and is easily rotated 180 degrees.
Serial LVDS pairs (OUTA+/- through OUTD+/-, CLKOUT+/-, FR+/-) must be routed as 100 ohm differential microstrip with intra-pair skew below 5 ps, plus matched lengths within ~0.5 mm across all eight pairs. Stagger section counters at the FPGA receiver to absorb small imbalances, but do not allow differential to single-ended adapters on the PCB route them as true LVDS directly into an FPGA LVDS input bank.
合規資訊
Pb-free #PBF suffix confirms RoHS compliance. The IUKG suffix indicates industrial temperature grade -40C to +85C. AEC-Q100 (automotive) is not applicable; the family targets communications/test-and-measurement applications.
