LTC2175IUKG-12 - 12-Bit 125Msps Quad ADC, Serial LVDS | ADI
N.º da peça: LTC2175IUKG-12 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $42.5 | $42,50 |
| 10 | $39.85 | $398,50 |
| 100 | $35.2 | $3.520,00 |
| 500 | $31.4 | $15.700,00 |
| 1.000 | $28.1 | $28.100,00 |
LTC2175IUKG-12 Visão geral
An ADC is a mixed-signal integrated circuit that converts continuous analog waveforms into discrete digital codes; pipelined ADCs specifically use a multi-stage switched-capacitor architecture to balance high sampling speed against moderate die area and power dissipation. The LTC2175 family sits inside the converter hierarchy as: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. It therefore serves wherever simultaneous multi-channel wide-bandwidth capture is needed, including communications baseband, radar, and instrumentation front ends.
Key features include ±0.3 LSB INL (typical) and ±0.1 LSB DNL (typical) with no missing codes over the full operating temperature range, plus a low 0.3 LSB RMS transition noise. The 52-pin QFN package provides a compact 7x8 mm footprint with an exposed pad (EP) that bonds the die substrate to PCB copper, lowering thermal resistance and improving high-temperature performance. Configuration is via SPI or a parallel mode-select interface, allowing trade-offs between sample rate, channel count, and output width.
Typical applications include diversity RF receivers, MIMO/Multi-IF downconverters, advanced wireless base stations, broadband wireless local loops, and portable test instrumentation. The quad-channel, simultaneous-sampling architecture is particularly well-suited to I/Q capture paths where phase coherence between channels is critical.
When designing in this device, allocate adequate ground returns and a solid ground pour on layer 2 beneath the QFN, and follow the analog input network shown in the datasheet (typically a small series damping resistor plus shunt capacitance) to control charge kickback at high input frequencies. Decouple AVDD and DVDD separately with low-ESR ceramics near the pins.
This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving the design engineer a single, decision-ready reference.
Alternativas drop-in para LTC2175IUKG-12 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com LTC2175IUKG-12 (mesmo formato e footprint) — diferindo em Package, Number of Channels, Resolution, Input Type, RoHS Status.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
LTC2174IUKG-12
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2173IUKG-12
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2175IUKG-14
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
LTC2175CUKG-14
✅ Drop-In✓ Em estoque
$60.7 / unidade
Ver ficha técnica →LTC2171IUKG-12
✅ Drop-In✓ Em estoque
$23.3 / unidade
Ver ficha técnica →LTC2172IUKG-12
✅ Drop-In✓ Em estoque
$33.1 / unidade
Ver ficha técnica →LTC2175IUKG-12 Classificações máximas e características elétricas
| Manufacturer | Analog Devices (formerly Linear Technology) |
| Part Number | LTC2175IUKG-12 |
| Resolução | 12 bits |
| Number of Channels | 4 (simultaneous sampling) |
| Taxa de amostragem | 125 Msps max |
| Architecture | Pipelined |
| INL (typical) | ±0.3 LSB |
| DNL (typical) | ±0.1 LSB |
| Missing Codes | None (over temperature) |
| Transition Noise | 0.3 LSB RMS |
| Digital Output Format | Serial LVDS (2-lane / 1-lane) |
| Input Type | Single-ended/differential analog |
| Encapsulamento | 52-QFN (7x8 mm) with exposed pad |
| Tipo de montagem | Surface Mount |
| Temperature Grade | Industrial |
| Faixa de temperatura de operação | -40C to +85C |
| Configuration Interface | SPI / parallel |
| RoHS | Compliant (Pb-free #PBF suffix) |
Configuração de pinos do LTC2175IUKG-12
| Pino 1 | SENSE — Analog input common-mode sense |
| Pino 2 | GND — Analog ground |
| Pino 3 | VDD — Analog supply (1.8 V typical) |
| Pino 4 | REFN — Negative reference decoupling |
| Pino 5 | REFP — Positive reference decoupling |
| Pino 6 | VREF — Reference output |
| Pino 7 | GND — Analog ground |
| Pino 8 | INA+ — Channel A positive analog input |
| Pino 9 | INA- — Channel A negative analog input |
| Pino 10 | INB+ — Channel B positive analog input |
| Pino 11 | INB- — Channel B negative analog input |
| Pino 12 | GND — Analog ground |
| Pino 13 | INC+ — Channel C positive analog input |
| Pino 14 | INC- — Channel C negative analog input |
| Pino 15 | IND+ — Channel D positive analog input |
| Pino 16 | IND- — Channel D negative analog input |
| Pino 17 | GND — Analog ground |
| Pino 18 | ENC+ — Encode input positive |
| Pino 19 | ENC- — Encode input negative |
| Pino 20 | GND — Clock ground |
| Pino 21 | OVDD — Output supply |
| Pino 22 | GND — Digital ground |
| Pino 23 | CS — SPI chip select |
| Pino 24 | SCK — SPI serial clock |
| Pino 25 | SDI — SPI serial data input |
| Pino 26 | SDO — SPI serial data output |
| Pino 27 | GND — Digital ground |
| Pino 28 | OUTA+ — LVDS data output channel A positive |
| Pino 29 | OUTA- — LVDS data output channel A negative |
| Pino 30 | OUTB+ — LVDS data output channel B positive |
| Pino 31 | OUTB- — LVDS data output channel B negative |
| Pino 32 | OUTC+ — LVDS data output channel C positive |
| Pino 33 | OUTC- — LVDS data output channel C negative |
| Pino 34 | OUTD+ — LVDS data output channel D positive |
| Pino 35 | OUTD- — LVDS data output channel D negative |
| Pino 36 | GND — Digital ground |
| Pino 37 | MODE — Mode / lane selection |
| Pino 38 | OGND — LVDS output ground |
| Pino 39 | OVDD — Output supply |
| Pino 40 | CLKOUT+ — Clock output positive |
| Pino 41 | CLKOUT- — Clock output negative |
| Pino 42 | FR+ — Frame output positive |
| Pino 43 | FR- — Frame output negative |
| Pino 44 | OGND — LVDS ground |
| Pino 45 | OVDD — Output supply |
| Pino 46 | DNC — Do not connect |
| Pino 47 | DNC — Do not connect |
| Pino 48 | GND — Analog ground |
| Pino 49 | OVDD — Output supply |
| Pino 50 | DNC — Do not connect |
| Pino 51 | DNC — Do not connect |
| Pino 52 | GND — Analog ground |
Aplicações típicas
LTC2175IUKG-12 é adequado para 7 aplicaçãos: Diversity RF Receivers, MIMO / Multi-IF Downconverters, Wireless Base Station Receiver Cards, Broadband Wireless Local Loop, Portable Test Instrumentation, Radar and Lidar Digitiser Subsystems, Medical Imaging Receivers.
Diversity RF Receivers
The LTC2175IUKG-12's four simultaneous-sampling channels digitise the I/Q streams from two or more antenna branches at 125 Msps, preserving phase coherence required for diversity combining. The serial LVDS interface minimises board area while the 0.3 LSB RMS transition noise keeps SNR high in narrowband cellular links. Pin-compatible drop-in: LTC2174IUKG-12 (105 Msps) for cost-down when 125 Msps headroom is not required.
Recomendado
MIMO / Multi-IF Downconverters
Each of the four input channels can be fed from a separate IF chain after mixing, allowing a single LTC2175IUKG-12 to capture multiple intermediate frequencies in parallel at full 125 Msps. The pipelined architecture delivers ±0.3 LSB INL across temperature for clean demodulation of multi-carrier waveforms in 4G/5G base stations.
Recomendado
Wireless Base Station Receiver Cards
Baseband receivers for LTE and 5G front-end cards require wideband simultaneous capture of multiple antenna streams; the LTC2175IUKG-12 provides 4 channels @ 125 Msps with no missing codes, sustaining digital pre-distortion loops and beam-forming DSP. The 52-QFN exposed pad couples die heat to inner-layer copper, suitable for chassis-mounted boards.
Recomendado
Broadband Wireless Local Loop
Fixed-wireless and last-mile access points need four channels of synchronised 80-125 Msps conversion. The LTC2175IUKG-12's low 0.3 LSB RMS transition noise preserves digital modulation error vector magnitude (EVM) over OFDM waveforms with hundreds of carriers.
Recomendado
Portable Test Instrumentation
Battery-powered oscilloscopes, spectrum-analyser intermediate-IF cards, and signal-intelligence recorders benefit from the LTC2175IUKG-12's quad synchronous capture and serial LVDS outputs that isolate the digital switching noise from sensitive analog rails. Industrial -40C to +85C rating covers field-deployed instrument enclosures without additional thermal screening.
Recomendado
Radar and Lidar Digitiser Subsystems
Phase-coherent radar I/Q and pulsed lidar front-end boards use multi-channel synchronised ADCs; the LTC2175IUKG-12 returns four parallel samples at 125 Msps with sub-LSB noise, ideal for staring-array lidar aggregation and FMCW chirp capture. Its -40C to +85C rating suits outdoor and airborne enclosures without downgrading to military temperature grades.
Recomendado
Medical Imaging Receivers
Ultrasound beamformer front-end receivers digitise 4-32 channels at 40-125 Msps. With 4 channels per IC, a single LTC2175IUKG-12 services a sub-array, providing ±0.3 LSB INL linearity and 0.3 LSB RMS noise critical for low-amplitude echo capture. Its industrial temperature grade suits cart-based clinical equipment.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para LTC2175IUKG-12 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | LTC2174IUKG-12 | LTC2173IUKG-12 | LTC2175IUKG-14 | LTC2171IUKG-12 | LTC2172IUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-QFN (7x8) | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same | 52-QFN (7x8) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 14 bit | 12 bit | 12 bit |
| Sampling Rate | 125 Msps | 105 Msps | 80 Msps | 125 Msps | 65 Msps | 105 Msps |
| Channels | 4 (simultaneous) | 4 (simultaneous) | 4 (simultaneous) | 4 (simultaneous) | 4 (simultaneous) | 4 (simultaneous) |
| INL (typ) | ±0.3 LSB | ±0.3 LSB | ±0.3 LSB | ±0.5 LSB | ±0.3 LSB | ±0.3 LSB |
| Output Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
| Temperature Range | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Principais diferenciais
- Highest sample rate in the 12-bit LTC217x QFN-52 family (vs LTC2173IUKG-12)
- Quad-channel simultaneous sampling on a single ADC (vs AD9268XCPZ-125)
- Industrial temperature grade drop-in alternative path (vs LTC2175CUKG-14)
- Same package offers 14-bit upgrade path (vs LTC2175IUKG-14)
Notas de projeto
Reference the analog input network shown in the datasheet typically a 25 ohm series damping resistor followed by a few pF shunt capacitance right at the package pin. Inadequate damping at 125 Msps will allow the pipeline's charge-kickback transient to introduce integral non-linearity. Use a wide ground pour on layer 2 directly under the 52-QFN exposed pad to dissipate heat to the chassis or inner copper.
Decouple AVDD with a 1.0 uF X7R 0603 ceramic plus a 100 nF X7R 0402 in parallel, each within 2 mm of the pin. DVDD (or OVDD) for the LVDS I/O requires a separate ferrite bead plus 100 nF capacitor to suppress digital switching noise from leaking back into the analog rails. The datasheet recommends a 100 nF cap on REFP and a 1.0 uF on REFN to set the internal reference network.
Differential encode clock routing is mandatory; driving ENC with a single-ended TTL signal degrades sample-to-sample jitter from ~70 fs to >1 ps, destroying dynamic range. Keep ENC+/ENC- as a 100 ohm differential pair, length-matched to within 0.5 mm, and route away from analog input traces. Verify pin 1 orientation against the printed dot before PCB assembly; the QFN-52 has no obvious top-side identifier and is easily rotated 180 degrees.
Serial LVDS pairs (OUTA+/- through OUTD+/-, CLKOUT+/-, FR+/-) must be routed as 100 ohm differential microstrip with intra-pair skew below 5 ps, plus matched lengths within ~0.5 mm across all eight pairs. Stagger section counters at the FPGA receiver to absorb small imbalances, but do not allow differential to single-ended adapters on the PCB route them as true LVDS directly into an FPGA LVDS input bank.
Informações de conformidade
Pb-free #PBF suffix confirms RoHS compliance. The IUKG suffix indicates industrial temperature grade -40C to +85C. AEC-Q100 (automotive) is not applicable; the family targets communications/test-and-measurement applications.
