LTC2246HLU#PBF - 14-Bit 25Msps Low-Power ADC | Analog Devices
MPN： LTC2246HLU#PBF ✓ 啟用中LTC2246HLU#PBF 概覽
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts a continuous analog input voltage into a discrete digital code. Pipelined ADCs in particular use a multi-stage architecture with sample-and-hold front ends and per-stage flash sub-ADCs to achieve high sampling rates at moderate power. Within the power-management and data-acquisition hierarchy, this part sits in the signal path - ADC - data-converter - mixed-signal IC family, providing the bridge between analog front-ends (LNAs, filters, drivers) and a downstream DSP, FPGA, or microcontroller.
Key specifications include a flexible 1 Vp-p to 2 Vp-p input range, 575 MHz full-power input bandwidth, ±1 LSB (typical) integral non-linearity, ±0.5 LSB differential non-linearity, and an integrated sample-and-hold amplifier with a clock-duty-cycle stabilizer. Power consumption is typically 75 mW at 25 Msps from a single 3V supply, and shutdown/nap modes reduce dissipation further for power-sensitive designs. The 32-pin TQFP-32 (5x5 mm) plastic package supports surface-mount assembly and is pin-compatible with the broader LTC2246/47/48 family.
Applications include high-end imaging, communications transceivers, instrumentation, and any signal chain that needs 14-bit dynamic range at moderate sampling rates. The wide input bandwidth allows undersampling of IF signals in communications systems.
When designing with this part, ensure the analog input is properly driven by a differential amplifier or transformer, and decouple AVDD and OVDD pins separately. The clock-duty-cycle stabilizer relaxes clock-source requirements, but jitter still directly impacts SNR - use a low-jitter oscillator.
This page synthesizes distributor pricing, application examples, and pin-compatible family members that go beyond the datasheet's typical-application circuit.
直接替換替代品，適用於 LTC2246HLU#PBF — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： LTC2246HLU#PBF （相同外形與佔位） — 差異在於 Resolution, SNR, Sample Rate, SFDR, Architecture.
LTC2247HLU#PBF
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
LTC2248HLU#PBF
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
LTC2246IUH#PBF
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
LTC2226HLU#PBF
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →LTC2245IUH
✅ 直接替換聯絡詢價
查看資料表 →LTC2246HLU#PBF 最大額定值與電氣特性
| 解析度 | 14 bit |
| Sample Rate | 25 Msps |
| Number of Input Channels | 1 |
| ADC Type | Pipelined |
| Input Type | Differential, Single-Ended |
| Data Interface | Parallel |
| SNR | 74.3 dB at Nyquist |
| SFDR | 90 dB at Nyquist |
| INL (Integral Non-Linearity) | ±1 LSB (typ) |
| DNL (Differential Non-Linearity) | ±0.5 LSB (typ) |
| Full-Power Input Bandwidth | 575 MHz |
| 輸入電壓範圍 | 1 Vp-p to 2 Vp-p |
| 供應電壓 | 3 V (single) |
| Power Consumption | 75 mW at 25 Msps (typ) |
| 工作溫度範圍 | -40C to +125C |
| 封裝 | 32-TQFP (5 mm x 5 mm) |
| 安裝類型 | Surface Mount |
| Automotive Grade (H grade) | Yes - H suffix indicates automotive temperature grade |
LTC2246HLU#PBF 腳位配置
| 腳位 1 | AVDD — Analog 3V supply |
| 腳位 2 | IN+ — Differential analog input positive |
| 腳位 3 | IN- — Differential analog input negative |
| 腳位 4 | VCM — Common-mode voltage bypass |
| 腳位 5 | GND — Analog ground |
| 腳位 6 | SENSE — Input range select |
| 腳位 7 | REFT — Top reference decoupling |
| 腳位 8 | REFB — Bottom reference decoupling |
| 腳位 9 | AVDD — Analog 3V supply |
| 腳位 10 | GND — Analog ground |
| 腳位 11 | CLK — Clock input |
| 腳位 12 | CLKOUT- — Complementary clock output |
| 腳位 13 | CLKOUT+ — True clock output |
| 腳位 14 | OGND — Output driver ground |
| 腳位 15 | OVDD — Output driver 3V supply |
| 腳位 16 | D13 — Data output bit 13 (MSB) |
| 腳位 17 | D12 — Data output bit 12 |
| 腳位 18 | D11 — Data output bit 11 |
| 腳位 19 | D10 — Data output bit 10 |
| 腳位 20 | D9 — Data output bit 9 |
| 腳位 21 | D8 — Data output bit 8 |
| 腳位 22 | D7 — Data output bit 7 |
| 腳位 23 | D6 — Data output bit 6 |
| 腳位 24 | D5 — Data output bit 5 |
| 腳位 25 | D4 — Data output bit 4 |
| 腳位 26 | D3 — Data output bit 3 |
| 腳位 27 | D2 — Data output bit 2 |
| 腳位 28 | D1 — Data output bit 1 |
| 腳位 29 | D0 — Data output bit 0 (LSB) |
| 腳位 30 | OF — Overflow output |
| 腳位 31 | MODE — Output mode / shutdown |
| 腳位 32 | AVDD — Analog 3V supply |
典型應用
LTC2246HLU#PBF 適用於 6 應用s: Digital Imaging Front-End, Communications Receiver IF Sampling, Portable Test Instruments, Ultrasound Imaging Signal Path, Industrial Data Acquisition Systems, Radar and Lidar Signal Processing.
Digital Imaging Front-End
The LTC2246HLU#PBF fits digital imaging pipelines that need 14-bit dynamic range at moderate bandwidth. Its 74.3 dB SNR and 90 dB SFDR at Nyquist - combined with the 575 MHz full-power input bandwidth - capture high-contrast image sensor outputs without smear or aliasing. The pipelined 14-bit architecture delivers the bit depth required for high-quality medical and machine-vision imaging while keeping power dissipation around 75 mW at 25 Msps, easing thermal design in compact camera modules.
推薦
Communications Receiver IF Sampling
The LTC2246HLU#PBF suits communications receiver IF sampling because of its 575 MHz input bandwidth, which supports undersampling of intermediate frequencies well above the Nyquist limit. Its 14-bit resolution and 74.3 dB SNR deliver the dynamic range needed for digital downconversion in cellular base stations and software-defined radios. The differential input topology rejects common-mode noise from mixers and LO leakage, while the parallel CMOS output interfaces cleanly with FPGAs and DSPs.
推薦
Portable Test Instruments
The LTC2246HLU#PBF serves handheld and bench-top test equipment that demands 14-bit precision at 25 Msps without draining battery. Its 75 mW typical power consumption plus shutdown/nap modes enables long operating life in portable oscilloscopes and spectrum analyzers. The H-grade -40C to +125C temperature range supports outdoor and industrial field use, while the small 5x5 mm TQFP-32 footprint frees PCB real estate for analog front-end components.
推薦
Ultrasound Imaging Signal Path
The LTC2246HLU#PBF addresses ultrasound receiver channels that need 14-bit dynamic range at sample rates compatible with 5-15 MHz transducer frequencies. Its 90 dB SFDR enables detection of small echoes adjacent to large reflected signals, while the 575 MHz bandwidth supports time-gain-compensated beamformer inputs. The differential architecture and integrated S/H reduce board complexity for multi-channel receiver designs.
推薦
Industrial Data Acquisition Systems
The LTC2246HLU#PBF works in industrial data-acquisition front-ends digitizing multi-MHz sensor signals. With H-grade temperature range (-40C to +125C), it tolerates factory-floor conditions while the parallel CMOS interface feeds microcontrollers, FPGAs, or ASICs. The shutdown and nap modes reduce idle power, while the integrated S/H and clock-duty-cycle stabilizer simplify timing design.
推薦
Radar and Lidar Signal Processing
The LTC2246HLU#PBF handles radar and lidar baseband digitization where 14-bit dynamic range and 25 Msps suffice for return-signal analysis. Its pipelined core with integrated clock-duty-cycle stabilizer minimizes aperture-jitter degradation of short return pulses, and the 575 MHz input bandwidth permits direct sampling of IF outputs from radar receivers. The small TQFP-32 package fits densely packed multi-channel sensor boards.
推薦
推薦產品摘要
工程參考資料，適用於 LTC2246HLU#PBF — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | LTC2247HLU#PBF | LTC2248HLU#PBF | LTC2246IUH#PBF | LTC2226HLU#PBF | LTC2245IUH |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 32-TQFP (5x5 mm) | 32-TQFP (5x5 mm) - same | 32-TQFP (5x5 mm) - same | 32-TQFP (5x5 mm) - same | 32-TQFP (5x5 mm) - same | 32-TQFP (5x5 mm) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit (-2 bits, ~17% less dynamic range) | 14 bit |
| Sample Rate | 25 Msps | 40 Msps (+60%) | 65 Msps (+160%) | 25 Msps (same) | 25 Msps (same) | 10 Msps (-60%) |
| Operating Temperature | -40C to +125C (H-grade) | -40C to +125C (H-grade) | -40C to +125C (H-grade) | -40C to +85C (I-grade) | -40C to +125C (H-grade) | -40C to +85C (I-grade) |
| Full-Power Input Bandwidth | 575 MHz | 575 MHz (same family) | 575 MHz (same family) | 575 MHz (same) | 575 MHz (same family) | 575 MHz (same family) |
| Supply Voltage | 3 V | 3 V | 3 V | 3 V | 3 V | 3 V |
主要差異化特點
- Speed-up path to 40 Msps and 65 Msps in the same package (對比LTC2247HLU#PBF / LTC2248HLU#PBF)
- H-grade automotive temperature qualification (對比LTC2246IUH#PBF (I-grade))
- Pin compatibility with 12-bit LTC2226 for resolution scaling (對比LTC2226HLU#PBF)
設計說明
Place 0.1 uF ceramic decoupling capacitors as close as possible to each AVDD pin (pins 1, 9, 32) and each OGND connection. Separate analog (AVDD) and digital (OVDD) ground planes, joining them at a single point near the ADC to avoid digital switching noise coupling into sensitive analog inputs. A 10 uF bulk capacitor should be placed within 1 cm of the analog supply pins.
Drive the analog input differentially through a low-noise differential amplifier or transformer. Common-mode noise on IN+ and IN- directly degrades SNR. Maintain symmetric input traces with 50 ohm characteristic impedance and route the differential pair length-matched to within 1 mm to preserve the 90 dB SFDR. Place an anti-aliasing low-pass filter (LC or active) immediately before the ADC input with cutoff at the desired signal bandwidth.
Clock jitter directly degrades SNR by the relationship SNR = 20*log10(1/(2*pi*f_in*t_jitter)). For 14-bit performance at input frequencies near 12.5 MHz, the clock source must have jitter below 1 ps RMS - use a low-jitter crystal oscillator or dedicated clock generator rather than an FPGA-generated clock. When using shutdown/nap for power saving, ensure the wake-up settling time is accounted for in the system timing budget.
合規資訊
Lead-free per #PBF suffix. RoHS and REACH compliant per Linear Technology/Analog Devices documentation. AEC-Q100 status: not formally qualified to AEC-Q100, but H-grade automotive temperature range is offered.
