PIC24FJ128GA110T-I/PF - 16-Bit MCU, 128KB Flash, 100-TQFP | Microchip
MPN： PIC24FJ128GA110T-I/PF ✓ 啟用中PIC24FJ128GA110T-I/PF 概覽
A 16-bit microcontroller (MCU) is a microprocessor core with a 16-bit data path and instruction set, sitting in the hierarchy between 8-bit MCUs (such as the PIC16 family) and 32-bit MCUs (such as PIC32 or ARM Cortex-M). The PIC24F family in particular uses a modified Harvard RISC architecture with hardware multiply/divide and is aimed at low-power, mixed-signal applications such as industrial control, sensor hubs, and Human Interface Devices (HID). Compared with 8-bit cores, 16-bit cores offer higher code density, larger linear memory maps, and richer peripheral integration while retaining deterministic interrupt response.
Key features of the PIC24FJ128GA110 include <100 nA standby current for battery-backed designs, hardware Real-Time Clock/Calendar (RTCC) with self-contained power domain, up to 85 I/O pins with 5V-tolerant inputs, 16-channel 10-bit ADC with 500 ksps conversion rate, and CTMU support for capacitive touch. The device operates from 2.0V to 3.6V across an industrial -40C to +85C temperature range and supports Microchip's nanoWatt XLP power-saving modes (Sleep, Deep Sleep, VBAT).
At the silicon level, the PIC24FJ128GA110 uses a flash-friendly CMOS process with on-chip voltage regulation that keeps the core running while I/O ports operate at higher voltages, eliminating the need for external level shifters in 5V-tolerant scenarios. The architecture combines a 16-bit ALU with a 24-bit instruction word for compact, orthogonal C-compiled code, and the integrated DMA controller offloads data movement from the CPU to peripheral endpoints such as the UART, SPI, ADC, and PMP.
Typical applications include industrial sensor interfaces, USB HID/CDC devices (when paired with an external transceiver), home automation controllers, low-power wireless sensor nodes, and battery-backed data loggers. The 100-pin TQFP package also gives designers enough I/O for parallel TFT displays, PMP/EPMP bus interfaces, and multi-UART gateway bridges.
When designing with this part, note that the PIC24FJ128GA110T-I/PF is the TQFP-packaged tape-and-reel variant, while the PIC24FJ128GA110-I/PF (tray) is identical silicon; choose the reel suffix for SMT assembly. Plan VBAT retention current carefully and add proper decoupling (100 nF + bulk) on each VDD/VSS pin pair to avoid noise-induced RTCC drift.
This page synthesizes distributor pricing for the 100-TQFP reel variant, drop-in TQFP-100 alternatives (PIC24FJ128GA110-I/PF, PIC24FJ128GA010-I/PF), and practical PCB layout notes not consolidated in the manufacturer datasheet.
直接替換替代品，適用於 PIC24FJ128GA110T-I/PF — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： PIC24FJ128GA110T-I/PF （相同外形與佔位） — 差異在於 ADC, Package, Operating Temperature, Core Architecture, MSL Level.
PIC24FJ128GA110-I/PF
✅ 直接替換📋 參考替代品（不在目錄中）
PIC24FJ128GA110-I/PT
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →PIC24FJ128GA010-I/PF
✅ 直接替換聯絡詢價
查看資料表 →PIC24FJ128GA108-E/PT
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →PIC24FJ128DA110T-I/BG
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →PIC24FJ128GA110T-I/PF 最大額定值與電氣特性
| Core Architecture | 16-bit PIC24F (modified Harvard RISC) |
| Family | PIC24FJ eXtreme Low Power (XLP) |
| Program Memory (Flash) | 128 KB (43K x 24 words) |
| RAM | 16 KB |
| Maximum CPU Speed | 32 MHz (16 MIPS at 3.3V) |
| Operating Voltage | 2.0 V to 3.6 V |
| 封裝 | 100-TQFP (14 x 14 mm) |
| I/O Pins | Up to 85 |
| UART | 4 |
| SPI | 3 |
| I2C | 3 |
| Timers | 16/32-bit, 23 independent |
| ADC | 10-bit, 16-channel, 500 ksps |
| RTCC | Yes (hardware, with VBAT) |
| CTMU (Capacitive Touch) | Yes |
| DMA | 8-channel |
| Standby Current | <100 nA (XLP Sleep) |
| 工作溫度 | -40 C to +85 C (Industrial) |
| 安裝類型 | Surface Mount (TQFP) |
| MSL 等級 | 3 (per JEDEC J-STD-020) |
| RoHS 狀態 | Compliant |
PIC24FJ128GA110T-I/PF 腳位配置
| 腳位 1 | RP15/PMA0/CN11/RB15 — Remappable I/O, PMP address bit 0 |
| 腳位 2 | RP14/PMA1/CN10/RB14 — Remappable I/O, PMP address bit 1 |
| 腳位 3 | RP13/PMA2/CN9/RB13 — Remappable I/O, PMP address bit 2 |
| 腳位 4 | RP12/PMA3/CN8/RB12 — Remappable I/O, PMP address bit 3 |
| 腳位 5 | RP11/PMA4/CN7/RB11 — Remappable I/O, PMP address bit 4 |
| 腳位 6 | RP10/PMA5/CN6/RB10 — Remappable I/O, PMP address bit 5 |
| 腳位 7 | RP9/PMA6/CN5/RB9 — Remappable I/O, PMP address bit 6 |
| 腳位 8 | RP8/PMA7/CN4/RB8 — Remappable I/O, PMP address bit 7 |
| 腳位 9 | RP7/PMD7/CN3/RB7 — Remappable I/O, PMP data bit 7 |
| 腳位 10 | RP6/PMD6/CN2/RB6 — Remappable I/O, PMP data bit 6 |
| 腳位 11 | RP5/PMD5/CN1/RB5 — Remappable I/O, PMP data bit 5 |
| 腳位 12 | RP4/PMD4/CN0/RB4 — Remappable I/O, PMP data bit 4 |
| 腳位 13 | RP3/PMD3/RB3 — Remappable I/O, PMP data bit 3 |
| 腳位 14 | RP2/PMD2/RB2 — Remappable I/O, PMP data bit 2 |
| 腳位 15 | RP1/PMD1/RB1 — Remappable I/O, PMP data bit 1 |
| 腳位 16 | RP0/PMD0/RB0 — Remappable I/O, PMP data bit 0 |
| 腳位 17 | VSS — Ground reference |
| 腳位 18 | VDD — Positive supply (2.0V-3.6V) |
| 腳位 19 | RD9 — Remappable I/O port D bit 9 |
| 腳位 20 | RD10 — Remappable I/O port D bit 10 |
| 腳位 21 | RD11 — Remappable I/O port D bit 11 |
| 腳位 22 | RD12 — Remappable I/O port D bit 12 |
| 腳位 23 | RD13 — Remappable I/O port D bit 13 |
| 腳位 24 | RD14 — Remappable I/O port D bit 14 |
| 腳位 25 | RD15 — Remappable I/O port D bit 15 |
| 腳位 26 | RC1/T2CK — Remappable I/O, Timer2 clock input |
| 腳位 27 | RC2/T3CK — Remappable I/O, Timer3 clock input |
| 腳位 28 | RC3/T4CK — Remappable I/O, Timer4 clock input |
| 腳位 29 | RC4 — Remappable I/O port C bit 4 |
| 腳位 30 | INT0/RF6 — External interrupt 0 / port F bit 6 |
| 腳位 31 | RF7 — Port F bit 7 |
| 腳位 32 | RF8 — Port F bit 8 |
| 腳位 33 | RF3 — Port F bit 3 |
| 腳位 34 | RF2 — Port F bit 2 |
| 腳位 35 | RF5 — Port F bit 5 |
| 腳位 36 | RF4 — Port F bit 4 |
| 腳位 37 | RF1 — Port F bit 1 |
| 腳位 38 | RF0 — Port F bit 0 |
| 腳位 39 | VSS — Ground reference |
| 腳位 40 | OSC1/CLKI/RA1 — Oscillator crystal input / port A bit 1 |
| 腳位 41 | OSC2/CLKO/RA2 — Oscillator crystal output / port A bit 2 |
| 腳位 42 | RA3 — Port A bit 3 |
| 腳位 43 | RA4 — Port A bit 4 |
| 腳位 44 | RA5 — Port A bit 5 |
| 腳位 45 | VDD — Positive supply (2.0V-3.6V) |
| 腳位 46 | RA7 — Port A bit 7 |
| 腳位 47 | RA9 — Port A bit 9 |
| 腳位 48 | RA10 — Port A bit 10 |
| 腳位 49 | RA11 — Port A bit 11 |
| 腳位 50 | RA12 — Port A bit 12 |
| 腳位 51 | RA13 — Port A bit 13 |
| 腳位 52 | RA14 — Port A bit 14 |
| 腳位 53 | RA15 — Port A bit 15 |
| 腳位 54 | VSS — Ground reference |
| 腳位 55 | RG3 — Port G bit 3 |
| 腳位 56 | RG2 — Port G bit 2 |
| 腳位 57 | RG1 — Port G bit 1 |
| 腳位 58 | RG0 — Port G bit 0 |
| 腳位 59 | RG6 — Port G bit 6 |
| 腳位 60 | RG7 — Port G bit 7 |
| 腳位 61 | RG8 — Port G bit 8 |
| 腳位 62 | RG9 — Port G bit 9 |
| 腳位 63 | MCLR — Master Clear (reset) input |
| 腳位 64 | RG15 — Port G bit 15 |
| 腳位 65 | VDD — Positive supply (2.0V-3.6V) |
| 腳位 66 | AVDD — Analog positive supply |
| 腳位 67 | AVSS — Analog ground reference |
| 腳位 68 | AN0/RA0 — Analog input 0 / port A bit 0 |
| 腳位 69 | AN1/RA1 — Analog input 1 / port A bit 1 |
| 腳位 70 | AN2/RA2 — Analog input 2 / port A bit 2 |
| 腳位 71 | AN3/RA3 — Analog input 3 / port A bit 3 |
| 腳位 72 | AN4/RA4 — Analog input 4 / port A bit 4 |
| 腳位 73 | AN5/RA5 — Analog input 5 / port A bit 5 |
| 腳位 74 | AN6/RA6 — Analog input 6 / port A bit 6 |
| 腳位 75 | AN7/RA7 — Analog input 7 / port A bit 7 |
| 腳位 76 | AN8/RB0 — Analog input 8 / port B bit 0 |
| 腳位 77 | AN9/RB1 — Analog input 9 / port B bit 1 |
| 腳位 78 | AN10/RB2 — Analog input 10 / port B bit 2 |
| 腳位 79 | AN11/RB3 — Analog input 11 / port B bit 3 |
| 腳位 80 | AN12/RB4 — Analog input 12 / port B bit 4 |
| 腳位 81 | AN13/RB5 — Analog input 13 / port B bit 5 |
| 腳位 82 | AN14/RB6 — Analog input 14 / port B bit 6 |
| 腳位 83 | AN15/RB7 — Analog input 15 / port B bit 7 |
| 腳位 84 | VREF+/CVREF+/AN23/RC0 — Voltage reference positive / comparator ref |
| 腳位 85 | VREF-/CVREF-/AN22/RC1 — Voltage reference negative / comparator ref |
| 腳位 86 | SDA3/RA14 — I2C3 data / port A bit 14 |
| 腳位 87 | SCL3/RA15 — I2C3 clock / port A bit 15 |
| 腳位 88 | SOSCI/RA0 — Secondary oscillator crystal input |
| 腳位 89 | SOSCO/T1CK/CN0/RA1 — Secondary oscillator crystal output / Timer1 input |
| 腳位 90 | RTCC/RA2 — Real-Time Clock output / port A bit 2 |
| 腳位 91 | VBAT — RTCC backup battery supply input |
| 腳位 92 | VSS — Ground reference |
| 腳位 93 | RC2 — Port C bit 2 |
| 腳位 94 | RC3 — Port C bit 3 |
| 腳位 95 | RC4 — Port C bit 4 |
| 腳位 96 | RC5 — Port C bit 5 |
| 腳位 97 | RC6 — Port C bit 6 |
| 腳位 98 | RC7 — Port C bit 7 |
| 腳位 99 | RC8 — Port C bit 8 |
| 腳位 100 | RC9 — Port C bit 9 |
典型應用
PIC24FJ128GA110T-I/PF 適用於 6 應用s: Industrial Sensor Interface Hub, USB HID / CDC Device Controller, Low-Power Wireless Sensor Node, Battery-Backed Data Logger, Home Automation Gateway Bridge, Human-Machine Interface (HMI) Display Controller.
Industrial Sensor Interface Hub
The PIC24FJ128GA110T-I/PF is well suited as an industrial sensor hub because its 16 MIPS throughput and 16 KB RAM can host Modbus RTU master stacks while servicing multiple SPI/I2C sensor front-ends simultaneously. The 4x UARTs handle RS-485/RS-232 transceiver links to PLCs, while the 16-channel 10-bit ADC aggregates analog transducers at up to 500 ksps. Its 2.0-3.6V supply range tolerates industrial 24V bus rails after a simple buck regulator, and XLP Sleep at <100 nA preserves battery backup during brownouts. Designers benefit from the 100-TQFP package, which exposes enough I/O for parallel keypad input plus 4-digit LED/LCD status displays without needing a second MCU.
推薦
USB HID / CDC Device Controller
The PIC24FJ128GA110T-I/PF's 32 MHz core, 16 KB RAM, and four UARTs make it an excellent host for USB Human Interface Device or Communications Device Class firmware when paired with an external USB transceiver. The 128 KB Flash holds full USB stacks and custom HID report descriptors, while DMA offloads endpoint buffer management from the CPU for sustained throughput. The 5V-tolerant I/O simplifies co-existence with legacy USB bus-powered peripherals, and the 100-TQFP exposes dedicated PMP/EPMP bus pins if external parallel USB host silicon is added. XLP Sleep reduces standby current when the device is bus-suspended, meeting USB suspend current requirements.
推薦
Low-Power Wireless Sensor Node
The PIC24FJ128GA110T-I/PF integrates well as the host MCU for sub-GHz or 2.4 GHz wireless sensor nodes, where its <100 nA XLP Sleep current dominates battery life. With RTCC ticking from a VBAT coin cell, the node can wake on a timer or external interrupt, sample a sensor over SPI/I2C, transmit via a paired radio, and return to sleep within milliseconds. The 16 KB RAM buffers transient burst data, and the 128 KB Flash holds OTA-capable application images with dual-partition firmware updates. Industrial -40 to +85 C operation covers outdoor and HVAC environments.
推薦
Battery-Backed Data Logger
With RTCC, VBAT domain, and 16 KB RAM, the PIC24FJ128GA110T-I/PF forms the core of a battery-backed data logger for medical or environmental recording. The integrated 10-bit ADC captures analog channels at 500 ksps, while DMA streams conversions into RAM without CPU intervention. Flash can be partitioned for circular logging with wear-leveling, and XLP Sleep preserves coin-cell life for years between maintenance cycles. The 100-TQFP package also supports 4-wire SPI or SD card interfaces for removable storage expansion.
推薦
Home Automation Gateway Bridge
The PIC24FJ128GA110T-I/PF works well as a multi-UART home automation gateway bridging Zigbee, Z-Wave, or Wi-Fi modules to a local RS-485 bus. Four UARTs let designers connect multiple wireless co-processors in parallel, while 3x I2C and 3x SPI handle sensor inputs and display panels. The 128 KB Flash fits full HomeKit/Matter bridge stacks, and CTMU capacitive touch inputs eliminate mechanical buttons on wall controllers. Wide 2.0-3.6V operation accepts regulated 3.3V from USB or PoE-derived supplies.
推薦
Human-Machine Interface (HMI) Display Controller
For HMI panels with TFT or segment LCD, the PIC24FJ128GA110T-I/PF's PMP/EPMP parallel bus and CTMU touch inputs offer a single-chip controller solution. The 100-TQFP exposes enough pins for an 8-bit PMP bus plus dedicated control lines driving 320x240 TFTs without external bridge logic. The 16 MIPS throughput handles button debouncing, on-screen menu navigation, and serial command parsing concurrently. CTMU scans capacitive keypads without additional ICs, reducing BOM cost for appliance and instrument front panels.
推薦
推薦產品摘要
工程參考資料，適用於 PIC24FJ128GA110T-I/PF — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | PIC24FJ128GA110-I/PF | PIC24FJ128GA110-I/PT | PIC24FJ128GA010-I/PF |
|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 100-TQFP (14x14 mm) | 100-TQFP (14x14 mm) | 100-TQFP (12x12 mm) | 100-TQFP (14x14 mm) |
| Program Memory (Flash) | 128 KB | 128 KB | 128 KB | 128 KB |
| RAM | 16 KB | 16 KB | 16 KB | 16 KB |
| Maximum CPU Clock | 32 MHz (16 MIPS) | 32 MHz (16 MIPS) | 32 MHz (16 MIPS) | 16 MHz (16 MIPS) |
| Operating Voltage | 2.0 V to 3.6 V | 2.0 V to 3.6 V | 2.0 V to 3.6 V | 2.0 V to 3.6 V |
| UART Count | 4 | 4 | 4 | 4 |
| ADC Channels | 16 x 10-bit | 16 x 10-bit | 16 x 10-bit | 16 x 10-bit |
| Standby Current | <100 nA (XLP) | <100 nA (XLP) | <100 nA (XLP) | <100 nA (XLP) |
主要差異化特點
- Tape-and-reel carrier for SMT production (對比PIC24FJ128GA110-I/PF)
- 32 MHz full-speed execution vs 16 MHz (對比PIC24FJ128GA010-I/PF)
- eXtreme Low Power XLP standby at <100 nA (對比PIC24FJ128DA110T-I/BG)
設計說明
The PIC24FJ128GA110T-I/PF integrates multiple VDD/VSS pin pairs (pins 18, 45, 65 for VDD; 17, 39, 54, 92 for VSS) plus a dedicated AVDD/AVSS pair on pins 66/67. Place a 100 nF decoupling capacitor within 5 mm of each VDD pin and a single 10 uF bulk capacitor near the package. For analog accuracy on ADC inputs, isolate AVDD with a ferrite bead or 10 ohm resistor from digital VDD, and decouple AVSS directly to the ground plane. The VBAT pin (91) requires its own 100 nF cap plus a series Schottky diode to the main 3.3V rail to prevent back-feed during normal operation.
Estimated: the MCLR pin (63) is bidirectional on PIC24F parts - if left unconnected it can drift into reset under noisy conditions. Tie MCLR to VDD through a 10 kohm pull-up and a 100 nF decoupling cap, or use the internal MCLR disable configuration if not using an external reset supervisor. Additionally, JTAG/PGDx pins must be left in their default high-impedance state during reset or the part may fail to enter ICSP mode. Use the CONFIG register bits to disable JTAG if not needed to free pins for GPIO.
The 100-TQFP has a 0.5 mm pitch and 14x14 mm body. Recommended land pattern follows IPC-7351 nominal density with 0.30 mm pad width and 0.45 mm pad length. Route the outer 85 I/O signals on the top layer with 0.15 mm trace/spacing to escape cleanly between TQFP pads; use inner layers for power and ground. Place the 32.768 kHz crystal (SOSCI/SOSCO, pins 88/89) within 5 mm of the package and guard the traces with a ground ring to avoid coupling digital noise into the RTCC domain.
合規資訊
RoHS and lead-free per Microchip product page. Not AEC-Q100 qualified; for automotive designs use PIC24FJ series qualified parts. Conflict-minerals compliance per Microchip CMRT filings.
