PIC32MX130F128H-50I/MR - 50MHz 32-bit MCU, 128KB Flash | Microchip
MPN： PIC32MX130F128H-50I/MR ✓ 啟用中PIC32MX130F128H-50I/MR 概覽
A PIC32MX microcontroller is a 32-bit flash MCU family from Microchip that combines a MIPS M4K core with rich digital peripherals, suitable for connected embedded products, consumer devices, and industrial control. The PIC32MX130F128H-50I/MR is the lower-pin-count sibling in the family and targets cost-sensitive applications that still need 32-bit performance, DSP acceleration (single-cycle MAC), and ample code space. The M4K core architecture retains the PIC ecosystem's reputation for deterministic interrupt response while adding 32-bit register width and 83 DMIPS throughput at 50 MHz.
Key features highlighted in the Microchip datasheet include 128 KB single-cycle Flash, 16 KB SRAM, Peripheral Pin Select (PPS) for flexible signal routing, three I2S/SPI modules, a Parallel Master Port (PMP) with dual buffers for graphics or memory-mapped interfaces, an integrated 10-bit ADC, and CTMU for capacitive touch sensing. USB and CAN are not present on this device, so designers targeting those should look at the PIC32MX2xx/5xx siblings.
The device integrates 5 16-bit timers, 5 IC/OC/PWM channels, two I2C, two UART, and supports up to 49 digital I/O via PPS. The 64-QFN 9x9 mm package exposes most of the available peripherals and provides a thermal pad for improved heat dissipation in continuous-operation industrial environments.
Typical applications include low-cost HMI panels with small TFTs driven by PMP, consumer audio accessories using I2S, multi-protocol sensor hubs with UART and I2C bridges, capacitive touch keypads via CTMU, and small logic-replacement or protocol-bridging controllers. The wide industrial temperature range and 50 MHz headroom also suit factory sensor nodes and serial-bridge appliances.
When designing with this part, plan the PPS mapping early because PPS groups constrain which pins can be assigned to which peripherals. Always provide a 1uF + 0.1uF decoupling pair near each VDD pin and confirm that any high-frequency I/O traces are length-matched for SPI or I2S synchronous operation.
This page consolidates distributor pricing, same-family drop-in alternatives, and practical design notes not duplicated from the manufacturer datasheet, including cross-references to PIC32MX1XX/2XX/5XX 64/100-pin family siblings.
直接替換替代品，適用於 PIC32MX130F128H-50I/MR — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： PIC32MX130F128H-50I/MR （相同外形與佔位） — 差異在於 ADC, Operating Temperature, Package, Core Architecture, DMA Channels.
PIC32MX170F256H-50I/MR
✅ 直接替換📋 參考替代品（不在目錄中）
PIC32MX130F064H-50I/MR
✅ 直接替換📋 參考替代品（不在目錄中）
PIC32MX150F128H-50I/MR
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
PIC32MX130F128H-I/MR
✅ 直接替換聯絡詢價
查看資料表 →PIC32MX130F128H-50I/MR 最大額定值與電氣特性
| Core Architecture | MIPS32 M4K 32-bit RISC |
| Maximum CPU Frequency | 50 MHz |
| DMIPS Performance | 83 DMIPS |
| Program Flash | 128 KB (128K x 8) |
| SRAM | 16 KB |
| 封裝 | 64-QFN (MR) 9x9 mm with exposed pad |
| Operating Voltage | 2.3 V to 3.6 V |
| 工作溫度 | -40 C to +85 C (Industrial) |
| I/O Pins | Up to 49 (with PPS) |
| ADC | 10-bit, up to 13 channels |
| Timers | 5 x 16-bit |
| Input Capture / Output Compare / PWM | 5 channels |
| UART | 2 |
| SPI | 3 (including I2S-capable) |
| I2C | 2 |
| PMP (Parallel Master Port) | Yes, with dual buffers |
| CTMU (Capacitive Touch) | Yes |
| Peripheral Pin Select (PPS) | Yes |
| DMA | Yes |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
PIC32MX130F128H-50I/MR 腳位配置
| 腳位 1 | RG15 — General purpose I/O with PPS |
| 腳位 2 | RG12 — General purpose I/O |
| 腳位 3 | RG13 — General purpose I/O |
| 腳位 4 | RG14 — General purpose I/O |
| 腳位 5 | VDD — Digital supply 2.3-3.6 V |
| 腳位 6 | RC1 — General purpose I/O / AN |
| 腳位 7 | RC2 — General purpose I/O / AN |
| 腳位 8 | RC3 — General purpose I/O / AN |
| 腳位 9 | RC4 — General purpose I/O / AN |
| 腳位 10 | RC5 — General purpose I/O / AN |
| 腳位 11 | VSS — Ground reference |
| 腳位 12 | RD0 — General purpose I/O |
| 腳位 13 | RD1 — General purpose I/O |
| 腳位 14 | RD2 — General purpose I/O / PMD |
| 腳位 15 | RD3 — General purpose I/O / PMD |
| 腳位 16 | RD4 — General purpose I/O / PMD |
| 腳位 17 | RD5 — General purpose I/O / PMD |
| 腳位 18 | RD6 — General purpose I/O / PMD |
| 腳位 19 | RD7 — General purpose I/O / PMD |
| 腳位 20 | VSS — Ground reference |
| 腳位 21 | RB0 — General purpose I/O / PGED |
| 腳位 22 | RB1 — General purpose I/O / PGEC |
| 腳位 23 | RB2 — General purpose I/O / AN |
| 腳位 24 | RB3 — General purpose I/O / AN |
| 腳位 25 | RB4 — General purpose I/O / AN |
| 腳位 26 | RB5 — General purpose I/O / AN |
| 腳位 27 | RB6 — General purpose I/O / AN |
| 腳位 28 | RB7 — General purpose I/O / AN |
| 腳位 29 | RB8 — General purpose I/O / AN |
| 腳位 30 | RB9 — General purpose I/O / AN |
| 腳位 31 | RB10 — General purpose I/O / AN |
| 腳位 32 | RB11 — General purpose I/O / AN |
| 腳位 33 | RB12 — General purpose I/O / AN |
| 腳位 34 | RB13 — General purpose I/O / AN |
| 腳位 35 | RB14 — General purpose I/O / AN |
| 腳位 36 | RB15 — General purpose I/O / AN |
| 腳位 37 | VSS — Ground reference |
| 腳位 38 | VDD — Digital supply 2.3-3.6 V |
| 腳位 39 | RF0 — General purpose I/O |
| 腳位 40 | RF1 — General purpose I/O |
| 腳位 41 | RF2 — General purpose I/O |
| 腳位 42 | RF3 — General purpose I/O |
| 腳位 43 | RF4 — General purpose I/O |
| 腳位 44 | RF5 — General purpose I/O |
| 腳位 45 | RF6 — General purpose I/O / IC |
| 腳位 46 | RF7 — General purpose I/O / IC |
| 腳位 47 | RF8 — General purpose I/O / IC |
| 腳位 48 | VDD — Digital supply 2.3-3.6 V |
| 腳位 49 | RG6 — General purpose I/O |
| 腳位 50 | RG7 — General purpose I/O |
| 腳位 51 | RG8 — General purpose I/O |
| 腳位 52 | RG9 — General purpose I/O |
| 腳位 53 | MCLR — Master clear reset (active low) |
| 腳位 54 | RE0 — General purpose I/O / PMD |
| 腳位 55 | RE1 — General purpose I/O / PMD |
| 腳位 56 | RE2 — General purpose I/O / PMD |
| 腳位 57 | RE3 — General purpose I/O / PMD |
| 腳位 58 | RE4 — General purpose I/O / PMD |
| 腳位 59 | RE5 — General purpose I/O / PMD |
| 腳位 60 | RE6 — General purpose I/O / PMD |
| 腳位 61 | RE7 — General purpose I/O / PMD |
| 腳位 62 | AVDD — Analog supply 2.3-3.6 V |
| 腳位 63 | AVSS — Analog ground |
| 腳位 64 | EP — Exposed thermal pad - connect to VSS |
典型應用
PIC32MX130F128H-50I/MR 適用於 6 應用s: Low-Cost HMI with PMP-driven LCD, Consumer Audio Accessory with I2S Codec, Multi-Protocol Industrial Sensor Hub, Capacitive Touch Keypad with CTMU, Serial Protocol Bridge / UART-SPI-I2C Gateway, Small Logic Replacement / Glue Controller.
Low-Cost HMI with PMP-driven LCD
The PIC32MX130F128H-50I/MR suits monochrome and low-color GLCD human-machine interfaces because its Parallel Master Port exposes 8/16-bit data with separate read/write strobes and dual buffers, removing DMA strain during display refresh. The 50 MHz M4K core executes pixel-font rendering and button scanning in real time while PPS routes keypad scan lines to any spare pin. With 16 KB of SRAM, the device holds a partial framebuffer or layered text widgets without external memory, and the 64-QFN exposed pad dissipates heat in always-on industrial panels.
推薦
Consumer Audio Accessory with I2S Codec
The PIC32MX130F128H-50I/MR's three I2S/SPI modules enable direct connection to a stereo audio codec such as an S/PDIF transmitter or a low-cost DAC, supporting sample rates up to 48 kHz from the M4K core's single-cycle MAC. Single-cycle multiply-accumulate accelerates software volume scaling and simple DSP blocks (EQ, limiting) without an external DSP. The 128 KB Flash accommodates USB HID or Bluetooth-classic control stacks paired with a UART-attached BT module, and the 64-QFN package is small enough for wearable or portable enclosures.
推薦
Multi-Protocol Industrial Sensor Hub
The PIC32MX130F128H-50I/MR aggregates multiple sensor interfaces - 2 UART, 2 I2C, and 3 SPI - making it ideal as a protocol-bridging hub between Modbus RTU RS-485 slaves and an upstream Ethernet or CAN gateway. Its 10-bit ADC with 13 channels handles analog 4-20 mA loop inputs, while the 50 MHz core runs PID loops at update rates well above 1 kHz. The industrial -40 to +85 C rating and 64-QFN footprint allow direct PCB mounting inside IP65 enclosures without thermal concerns.
推薦
Capacitive Touch Keypad with CTMU
The PIC32MX130F128H-50I/MR integrates Microchip's CTMU (Charge Time Measurement Unit), enabling up to 13 capacitive touch channels without an external touch controller. The M4K core runs the touch-scan scheduler and debounces while leaving cycles for backlight PWM, haptics, and USB-CDC serial output to a host. The 64-QFN 9x9 mm package mounts directly under a touch PCB or flex tail, and the industrial temperature rating supports appliance and automotive cabin controls.
推薦
Serial Protocol Bridge / UART-SPI-I2C Gateway
As a serial gateway, the PIC32MX130F128H-50I/MR can run up to 2 UART, 2 I2C, and 3 SPI interfaces concurrently thanks to PPS, mapping any function to most digital pins. The 50 MHz core executes command parsing, checksum validation (CRC-16/32), and protocol conversion without flow-control stalls. Designers commonly use this part to bridge legacy RS-232 equipment to modern SPI sensors or to expose I2C peripherals over USB-CDC via a UART-USB bridge chip.
推薦
Small Logic Replacement / Glue Controller
When a discrete CPLD or several 74-series logic ICs are replaced to save board area and BOM cost, the PIC32MX130F128H-50I/MR often fits the role because PPS remaps any peripheral function to any I/O pin and the M4K core executes custom glue logic with deterministic 50 MHz timing. The 128 KB Flash stores firmware-defined state machines, watchdogs, and timing patterns, while the 16 KB SRAM provides working memory for serial buffers and command queues. The 64-QFN package consolidates tens of logic functions into one IC.
推薦
推薦產品摘要
工程參考資料，適用於 PIC32MX130F128H-50I/MR — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | PIC32MX170F256H-50I/MR | PIC32MX130F064H-50I/MR | PIC32MX150F128H-50I/MR | PIC32MX130F128H-I/MR |
|---|---|---|---|---|---|
| Package | 64-QFN (MR) 9x9 mm | 64-QFN (MR) 9x9 mm | 64-QFN (MR) 9x9 mm | 64-QFN (MR) 9x9 mm | 64-QFN (MR) 9x9 mm |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit | MIPS32 M4K 32-bit |
| Max Frequency | 50 MHz | 50 MHz | 50 MHz | 50 MHz | 50 MHz |
| Flash | 128 KB | 256 KB | 64 KB | 128 KB | 128 KB |
| SRAM | 16 KB | 64 KB | 16 KB | 32 KB | 16 KB |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Industrial -40C to +85C | Commercial 0C to +70C |
| USB | No | No (170H variant) | No | No (150H variant) | No |
| PMP | Yes | Yes | Yes | Yes | Yes |
主要差異化特點
- Doubling Flash headroom without PCB changes (對比PIC32MX130F064H-50I/MR)
- Higher SRAM for graphical framebuffers (對比PIC32MX130F128H-I/MR)
- Step-up path with no footprint change (對比PIC32MX130F064H-50I/MR)
設計說明
Place a 10 uF bulk capacitor plus 0.1 uF decoupling capacitor as close as possible to each VDD/AVDD pair of the PIC32MX130F128H-50I/MR. The internal voltage regulator draws brief high-current pulses during Flash programming and peripheral activity, and inadequate decoupling causes brown-out resets that look like firmware bugs. Use short, wide traces or a dedicated power pour for VDD/VSS, and connect the QFN exposed pad (pin 64) to a continuous ground plane to provide both thermal dissipation and low-impedance return.
Route MCLR with a 10 kohm pull-up to VDD and place a 100 nF cap to ground close to the MCLR pin; this prevents spurious resets during in-circuit serial programming (ICSP) and power-up. PGEDx/PGECx lines should be as short as possible and not routed near switching signals to keep ICSP noise-free. For QFN packages, use 4-layer PCB with continuous ground plane under the device to provide thermal relief and signal reference.
Plan the Peripheral Pin Select (PPS) mapping before laying out the PCB. PPS groups restrict which peripheral functions can be assigned to which pins; remapping after design is possible in firmware but a poor initial pin assignment wastes I/O. Use the Microchip PPS configurator (part of MPLAB X) to validate the chosen pin map. For SPI and I2S, length-match clock and data lines to within 50 mil to avoid timing violations at 50 MHz peripheral clock.
Do not enable the on-chip voltage regulator's BOR (brown-out reset) at the lowest voltage unless required; many PIC32MX design issues trace to BOR triggering under momentary inrush current. Configure the device configuration bits (DEVCFG) carefully because mistakes cannot be changed in software without a programmer. The CTMU pins must be calibrated per board - stray capacitance from adjacent traces causes large touch sensitivity drift between prototypes.
合規資訊
RoHS and lead-free per Microchip product environmental compliance. Industrial temperature -40C to +85C. Not AEC-Q100 qualified - choose PIC32MX1XX automotive variants for automotive applications.