SI5332A-C-GM1 - 6-Output Any-Frequency Clock Generator, 333.33 MHz | Skyworks
MPN： SI5332A-C-GM1 ✗ 停產SI5332A-C-GM1 概覽
What is an any-frequency clock generator? It is a PLL-based timing IC that can produce multiple output frequencies from a single reference, replacing multiple crystal oscillators and fixed-frequency PLLs. Within the broader silicon timing hierarchy, any-frequency clock generators sit above fixed-frequency XO/VCXO parts and below full-blown network synchronizers; they are a sub-category of clock generators within the clock-and-timing IC family.
Key features include a differential output frequency range of 5 MHz to 333.33 MHz, integrated MultiSynth fractional dividers alongside high-speed integer dividers, RMS phase jitter performance as low as 190 fs (12 kHz to 20 MHz), dual spread-spectrum capability for EMI reduction, and up to 5 user-defined hardware input pins that can be assigned as output enable, frequency control, spread-spectrum enable, or input-reference selection. Free-run operation is supported via an external crystal or optional internal crystal, with PLL lock to an external reference clock as an alternative.
The MultiSynth architecture is the core technical innovation: each output bank uses a fractional-N divider that allows arbitrary non-integer frequency ratios without the integer-boundary spurs common to traditional PLLs. Combined with the high-PSRR internal regulators and low-dropout core, this yields deterministic jitter performance that is largely independent of the chosen output frequency, simplifying timing-budget analysis across multi-rate designs.
Typical applications include switch and router line-card clocks, server and storage timing, FPGA fabric and transceiver reference clocks, industrial Ethernet switches, and broadcast video. The wide output range covers common telecom rates (156.25 MHz, 161.13 MHz, 312.5 MHz), PCIe, Ethernet, and SDI video clocks from a single device.
When designing with this part, follow the Si5332 Reference Manual PCB-layout recommendations to achieve the rated jitter performance - especially short, symmetric differential traces and a clean ground reference under the exposed pad. Decoupling should follow the datasheet's reference schematic exactly.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a faster path to a working BOM.
直接替換替代品，適用於 SI5332A-C-GM1 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： SI5332A-C-GM1 （相同外形與佔位） — 差異在於 Divider Architecture, Function, Operating Temperature Range, Package, Supply Voltage.
SI5332A-D-GM1
✅ 直接替換聯絡詢價
查看資料表 →SI5332A-C-GM1R
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
SI5332A-B-GM1
✅ 直接替換📋 參考替代品（不在目錄中）
SI5332A-C-GM1 規格
| 功能 | Clock Generator |
| Series | MultiSynth |
| 輸出數量 | 6 |
| Output Frequency Range | 5 MHz to 333.33 MHz |
| Input Frequency Range (Differential) | 10 MHz to 250 MHz |
| RMS Phase Jitter (12 kHz to 20 MHz) | 190 fs (typical) |
| Output Logic | CML, HCSL, LVCMOS, LVDS, LVPECL (multi-format) |
| Divider Architecture | MultiSynth fractional + integer |
| 供應電壓 | 1.8 V / 2.5 V / 3.3 V core; separate output supply |
| 工作溫度範圍 | -40 C to +85 C (industrial) |
| 封裝 | 32-VFQFN Exposed Pad (5 x 5 mm) |
| 安裝類型 | Surface Mount |
| Spread Spectrum | Dual spread spectrum support |
| Hardware Input Pins | Up to 5 user-defined (OE, frequency select, SS enable, ref select) |
| RoHS 狀態 | Compliant |
SI5332A-C-GM1 腳位配置
| 腳位 1 | XA / FIN1 — Crystal input or external reference 1 |
| 腳位 2 | XB / FIN2 — Crystal input or external reference 2 |
| 腳位 3 | VDD_DIG — Digital core supply (1.8 V) |
| 腳位 4 | GND_DIG — Digital core ground |
| 腳位 5 | SDA — I2C serial data (configuration) |
| 腳位 6 | SCL — I2C serial clock (configuration) |
| 腳位 7 | VDD_IO — I/O supply (2.5 V or 3.3 V) |
| 腳位 8 | IN0 — Multi-function input pin 0 (OE / FSEL / SS_EN / REFSEL) |
| 腳位 9 | IN1 — Multi-function input pin 1 (OE / FSEL / SS_EN / REFSEL) |
| 腳位 10 | IN2 — Multi-function input pin 2 (OE / FSEL / SS_EN / REFSEL) |
| 腳位 11 | IN3 — Multi-function input pin 3 (OE / FSEL / SS_EN / REFSEL) |
| 腳位 12 | IN4 — Multi-function input pin 4 (OE / FSEL / SS_EN / REFSEL) |
| 腳位 13 | VDD_CORE — Core PLL supply (1.8 V) |
| 腳位 14 | GND_CORE — Core PLL ground |
| 腳位 15 | OUT0_N — Differential output 0 negative (multi-format) |
| 腳位 16 | OUT0_P — Differential output 0 positive (multi-format) |
| 腳位 17 | VDDO0 — Output 0 driver supply (1.8/2.5/3.3 V) |
| 腳位 18 | OUT1_N — Differential output 1 negative |
| 腳位 19 | OUT1_P — Differential output 1 positive |
| 腳位 20 | VDDO1 — Output 1 driver supply |
| 腳位 21 | OUT2_N — Differential output 2 negative |
| 腳位 22 | OUT2_P — Differential output 2 positive |
| 腳位 23 | VDDO2 — Output 2 driver supply |
| 腳位 24 | OUT3_N — Differential output 3 negative |
| 腳位 25 | OUT3_P — Differential output 3 positive |
| 腳位 26 | VDDO3 — Output 3 driver supply |
| 腳位 27 | OUT4_N — Differential output 4 negative |
| 腳位 28 | OUT4_P — Differential output 4 positive |
| 腳位 29 | VDDO4 — Output 4 driver supply |
| 腳位 30 | OUT5_N — Differential output 5 negative |
| 腳位 31 | OUT5_P — Differential output 5 positive |
| 腳位 32 | VDDO5 — Output 5 driver supply |
| 腳位 33 | EPAD — Exposed thermal pad - solder to continuous ground plane |
典型應用
SI5332A-C-GM1 適用於 6 應用s: 10/25/40/100G Ethernet Switch and Router Line Cards, FPGA Transceiver and Fabric Reference Clocks, Industrial Ethernet Switches and Fieldbus Timing, Server and Storage System Timing, Broadcast Video and SDI Timing, Telecom Baseband and Wireless Infrastructure.
10/25/40/100G Ethernet Switch and Router Line Cards
The SI5332A-C-GM1 is purpose-built for data-center Ethernet timing, where a single line card often needs a 156.25 MHz reference for the PHY, 161.13 MHz for the MAC/serializer, and 25 MHz for the management plane. With 190 fs RMS jitter and 6 independently programmable outputs in one 32-VFQFN device, the part replaces 3-4 separate XO/PLL ICs. Multi-format output drivers (CML, HCSL, LVPECL) connect directly to the most common PHY reference-clock inputs without level translators.
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FPGA Transceiver and Fabric Reference Clocks
FPGAs typically need separate reference clocks for the transceiver (multi-GHz SerDes) and the fabric logic (100-300 MHz). The SI5332A-C-GM1 supplies both from one part: outputs 1-2 can drive transceiver reference pins via CML/LVPECL, while outputs 3-6 provide fabric clocks at LVCMOS logic levels. The MultiSynth fractional divider produces exact non-integer rates such as 161.1328125 MHz that integer PLLs cannot generate without frequency errors, simplifying FPGA transceiver-link training.
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Industrial Ethernet Switches and Fieldbus Timing
Industrial Ethernet protocols (PROFINET, EtherCAT, EtherNet/IP) and fieldbus standards require deterministic clocks with low jitter for synchronization to IEEE 1588 grandmasters. The SI5332A-C-GM1's -40 C to +85 C industrial temperature range and spread-spectrum option meet EMI compliance under EN 55022 Class B. A typical design uses one output at 50 MHz for the MAC, one at 25 MHz for the PHY reference, and one LVCMOS at 8 MHz for the microcontroller subsystem, all from a single IC.
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Server and Storage System Timing
Servers and RAID storage controllers require multiple clock domains: PCIe Gen4/5 reference (100 MHz HCSL), SAS expander clocks, BMC clocks, and memory subsystem timing. The SI5332A-C-GM1 supports HCSL output format natively for PCIe, while LVDS outputs drive memory buffers and LVCMOS outputs run the BMC microcontroller. Its 1.8/2.5/3.3 V flexible supplies integrate into standard server power rails without extra LDO regulators.
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Broadcast Video and SDI Timing
SDI video standards (SD-SDI, HD-SDI, 3G-SDI, 6G/12G-SDI) require fixed reference clocks at 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz with very low jitter to preserve eye-mask compliance. The SI5332A-C-GM1's fractional divider accuracy produces these exact rates with 0 ppm error, and the low RMS jitter ensures downstream PHYs pass SMPTE conformance tests. Multiple video output formats can be supported from a single timing IC.
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Telecom Baseband and Wireless Infrastructure
Telecom baseband cards need JESD204B/C subclass-1 clocks with deterministic latency and sub-ps jitter. The SI5332A-C-GM1 drives JESD204B converters directly with its low-jitter outputs, and the SYSREF output enables subclass-1 deterministic latency for ADCs and DACs in radio units. Its frequency flexibility means one part can serve both the baseband clock tree (122.88 MHz, 153.6 MHz) and the fronthaul Ethernet clock (156.25 MHz) without board rework.
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推薦產品摘要
工程參考資料，適用於 SI5332A-C-GM1 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | SI5332A-D-GM1 | SI5332A-C-GM1R | SI5332A-B-GM1 |
|---|---|---|---|---|
| Package | 32-VFQFN Exposed Pad (5 x 5 mm) | 32-VFQFN Exposed Pad (5 x 5 mm) - same | 32-VFQFN Exposed Pad (5 x 5 mm) - same | 32-VFQFN Exposed Pad (5 x 5 mm) - same |
| Brand | Skyworks Solutions | Skyworks Solutions - same | Skyworks Solutions - same | Skyworks Solutions - same |
| Number of Outputs | 6 | 6 | 6 | 8 |
| Max Output Frequency | 312.5 MHz | 333.33 MHz | 312.5 MHz | 333.33 MHz |
| RMS Jitter (12 kHz-20 MHz) | 190 fs | 190 fs | 190 fs | 190 fs |
| Divider Architecture | MultiSynth fractional + integer | MultiSynth fractional + integer | MultiSynth fractional + integer | MultiSynth fractional + integer |
| Pinout Compatibility | Reference pinout | Identical pinout in 5-312.5 MHz range | Identical pinout | Pins 21-28 differ (8 vs 6 outputs) |
| Lifecycle Status | Obsolete | Active (or NRND) | Obsolete (tape-and-reel variant of obsolete die) | Active |
| 1 kty Approx. Price (USD) | 12.50 | 13.20 | 12.80 | 16.40 |
主要差異化特點
- Multi-format output drivers eliminate external level translators (對比Fixed-format clock generators (e.g., SI5351 family))
- MultiSynth fractional divider enables true any-frequency synthesis (對比Integer-N PLL clock generators)
- Lowest jitter in its output-count class (對比Generic 6-output PLLs at similar cost)
設計說明
Follow the Si5332 Reference Manual PCB layout section exactly: the exposed thermal pad (pin 33) must be soldered to a continuous ground plane stitched with vias on a 1 mm grid. Differential output traces must be length-matched to within 2.5 mm to preserve the datasheet's jitter specification; place 100 nF X7R 0402 decoupling caps within 1 mm of each VDDO/VDD pin. The reference manual notes that deviating from these guidelines can degrade jitter by 2-3x, which can fail IEEE 802.3 25G transmitter masks.
Keep the XA/XB crystal traces short (less than 5 mm) and surround them with a ground pour; any noise coupling onto these traces appears directly as output jitter. If using an external reference clock instead of a crystal, route the reference on a 50-ohm controlled-impedance trace with a 50-ohm termination at the XA pin. Skyworks' ClockBuilder Pro tool exports the exact stack-up and routing recommendations for any given Si5332 variant.
A common mistake is treating the SI5332A-C-GM1 as fully drop-in compatible with the SI5332A-D-GM1 at all frequencies: above 312.5 MHz the -C variant cannot lock because the VCO/divider chain is programmed for the lower ceiling. Always check your highest required output frequency before substituting. Another common error is configuring output format (CML vs HCSL vs LVDS) via software but forgetting to bias the unused differential pin - this causes EMI and reduces output amplitude; the ClockBuilder Pro schematic generator flags this and inserts the correct bias network automatically.
合規資訊
RoHS and REACH compliance per Skyworks Si5332 product page. Not AEC-Q100 qualified (industrial temp range -40 to +85 C only); conflict-minerals compliance statement published by Skyworks/Silicon Labs. Halogen-free status was not stated in the verified web data and is set to unknown.
