MOSFET
产品（1294)
IQE008N03LM5CGATMA1 - 30V 253A OptiMOS 5 N-Channel MOSFET | Infineon
The Infineon IQE008N03LM5CGATMA1 is an N-channel OptiMOS 5 power MOSFET rated at 30 V drain-to-source voltage and 0.85 mOhm maximum on-resistance at 20 A and 10 V gate drive, housed in a 9-pin PG-TTFN-9-1 (8-PowerTDFN) wettable-flank surface-mount package. It delivers continuous drain current of 27 A at 25 C ambient and 253 A at case temperature (Tc), with total power dissipation of 2.1 W (Ta) and 89 W (Tc). Key figures of merit include 64 nC total gate charge at 10 V VGS and 5700 pF input capacitance at 15 V VDS, optimized for high-frequency switching conversion. The wettable-flank terminations enable automated optical inspection (AOI) of solder joints, a critical requirement for automotive and high-reliability industrial assemblies. A power MOSFET is a voltage-controlled semiconductor switch that uses an insulated-gate field-effect structure to modulate conduction between source and drain terminals. It belongs to the discrete semiconductor hierarchy: MOSFET -> transistor -> discrete semiconductor. Low-voltage MOSFETs such as this OptiMOS 5 part are widely used as synchronous rectification switches and buck/boost converter high-side or low-side elements, where their gate-charge and on-resistance determine switching and conduction losses respectively. The IQE008N03LM5CGATMA1 leverages Infineon's OptiMOS 5 technology platform to achieve an extremely low figure of merit (FOM = RDS(on) x QG), targeting high-frequency, high-current-density applications. Its ±16 V VGS rating gives strong margin against typical 10 V driver rails. The combination of 0.85 mOhm on-resistance and 89 W power dissipation supports very high pulse currents, making the device suitable for hot-swap and e-fuse circuits where the MOSFET must absorb inrush energy without latch-up. Typical applications include synchronous rectification in 12 V buck converters for server and telecom point-of-load (POL) rails, hot-swap controllers on 12 V backplanes, battery management system (BMS) protection in 1-4S Li-ion packs, USB-PD power delivery switching, motor drive H-bridges in 12-24 V systems, and automotive ECU load switches. The low on-resistance minimizes conduction loss while the small PG-TTFN-9-1 footprint maximizes power density. Designers should ensure adequate copper pour (at least 100 mm^2) under the exposed pad to achieve rated 89 W power dissipation, and gate-drive resistors in the 2-10 ohm range to suppress ringing. Per the manufacturer datasheet, all ratings assume case temperature held at the specified value; de-rating is required based on actual PCB thermal performance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
IQE008N03LM5CGSCATMA1 - 30V 0.85mOhm Dual N-MOSFET | Infineon
The Infineon IQE008N03LM5CGSCATMA1 is a dual N-channel OptiMOS 5 power MOSFET array rated at 30 V drain-source voltage, 0.85 mOhm maximum on-resistance at 10 V VGS, and 252 A continuous drain current per channel, housed in the surface-mount PG-WHTFN-9 (WHTFN) package with dual-side cooling. The device integrates two N-channel MOSFETs in a common-drain/common-source footprint designed for synchronous rectification, half-bridge stages, and high-current OR-ing applications where ultra-low RDS(on) and superior thermal performance are required. A power MOSFET is a voltage-controlled semiconductor switch used to efficiently route or regulate current in power-conversion circuits. The OptiMOS 5 family represents Infineon's fifth-generation trench MOSFET technology optimized for low on-resistance per unit area, low gate charge, and low figure-of-merit (FOM). Within the broader hierarchy, a MOSFET is a discrete semiconductor -> power transistor -> voltage-controlled switch -> building block of switched-mode power supplies (SMPS), motor drives, and battery protection. The dual MOSFET array form factor further reduces parasitic inductance between the two FETs by sharing a common package. Key features include a maximum drain-source voltage of 30 V, a continuous drain current of 252 A per channel at the case-temperature-limited rating, an ultra-low maximum RDS(on) of 0.85 mOhm at VGS=10 V, and a logic-level gate threshold that supports standard 10 V and potentially lower drive voltages. The PG-WHTFN-9 package features top-side and bottom-side thermal pads (dual cooling), enabling direct heat extraction from both PCB surfaces for high-density designs such as server VRMs and telecom bricks. Technically, the IQE008N03LM5 uses Infineon's latest-generation silicon trench process, achieving the 0.85 mOhm rating in a compact package without sacrificing avalanche ruggedness. The dual-die construction balances the two MOSFETs symmetrically so the array can be used in high-side/low-side roles. Compared with discrete MOSFETs of similar rating, the integrated array reduces loop inductance between the two switches and simplifies PCB layout. Typical applications include synchronous rectification in 12 V and 24 V SMPS, server and telecom DC-DC converters, hot-swap and OR-ing controllers, motor drive half-bridges, and battery management systems (BMS) where very low conduction loss is required at high currents. When designing with this part, ensure the gate driver can source/sink the Qg charge and that adequate thermal vias connect both the top and bottom exposed pads to inner copper planes. The 30 V absolute maximum demands strict layout discipline when used near 24 V input rails with transients. This page synthesizes distributor pricing, parametric data from the Infineon datasheet, drop-in alternatives in the same PG-WHTFN-9 footprint, and practical design notes not consolidated in the manufacturer datasheet.
IQE008N03LM5SCATMA1 - 30V 0.85mΩ N-Ch MOSFET, PG-WHSON-8
The Infineon IQE008N03LM5SCATMA1 is an N-channel power MOSFET built on Infineon's OptiMOS 5 30 V technology platform, offering an ultra-low on-resistance of 0.85 mΩ in a Source-Down PG-WHSON-8 surface-mount package. It is rated for 30 V drain-source breakdown voltage and supports continuous drain current up to 252 A, making it suitable for high-current, low-voltage DC/DC conversion. The Source-Down package places the die thermal pad on the bottom of the device for direct dual-side cooling to the PCB, reducing junction-to-ambient thermal resistance in densely populated SMPS designs. A power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled switch used to efficiently route and regulate current in power conversion circuits. The OptiMOS 5 family from Infineon represents the fifth generation of trench MOSFET technology, optimized for low RDS(on), low gate charge, and high switching frequencies. The IQE008N03LM5SCATMA1 belongs to this family at the 30 V node, designed for synchronous rectification in switched-mode power supplies (SMPS), telecom point-of-load converters, and high-current battery protection circuits. Key features of the IQE008N03LM5SCATMA1 include a maximum RDS(on) of 0.85 mΩ at VGS = 10 V, a 2 V typical gate threshold voltage, and Source-Down packaging that flips the silicon die so the source potential is bonded to the large bottom pad. This construction lowers parasitic source inductance, improves thermal dissipation, and enables shorter high-current loops on the PCB. The device supports standard 10 V gate drive and is qualified for industrial-grade operating conditions. The Source-Down architecture simplifies PCB layout by exposing the thermal pad on the source side rather than the drain side, allowing direct attachment to a grounded copper pour for both thermal and electrical return. Compared to traditional drain-down DFN packages, this arrangement enables higher continuous current handling and improved EMI performance by reducing the high-current loop area. Infineon's OptiMOS 5 process also reduces figure-of-merit (FOM = RDS(on) × Qg) for higher switching frequency operation above 500 kHz. Typical applications for the IQE008N03LM5SCATMA1 include synchronous rectification in 12 V buck converters for server and telecom point-of-load rails, high-current hot-swap circuits in 24 V industrial bus systems, battery management protection FETs in 4S-8S Li-ion packs, USB-PD sink power paths, and motor drive half-bridges in low-voltage robotics. The Source-Down dual-side cooling is particularly valuable in slim-profile blade servers and 1U telecom equipment where top-side cooling is unavailable. When designing with this MOSFET, place a 10 nF to 100 nF ceramic bypass capacitor close to the gate pin to suppress parasitic turn-on from Miller coupling. For high-current applications, ensure the PCB copper area on both source and drain pads is sufficient to carry the continuous current without exceeding 25 °C temperature rise. Use VGS = 10 V drive to achieve the datasheet 0.85 mΩ RDS(on); with VGS = 4.5 V the on-resistance increases approximately 1.4× to 1.2 mΩ. This page synthesizes distributor stock and pricing, drop-in alternatives verified against the same PG-WHSON-8 footprint, and practical design notes not consolidated on the manufacturer datasheet.
IQE012N03LM5CGATMA1 - 30V 224A OptiMOS 5 N-FET | Infineon
The Infineon IQE012N03LM5CGATMA1 is an N-channel OptiMOS 5 low-voltage power MOSFET rated 30 V with 1.20 mOhm typical RDS(on) in an innovative PQFN 3.3x3.3 Source-Down center-gate package, supporting 224 A pulsed drain current (Tc) and 34 A continuous (Ta). It is built around an OptiMOS 5 trench process that minimizes gate charge, output charge and on-state losses, while the Source-Down architecture flips the silicon die so the source potential is bonded directly to the PCB thermal pad, dramatically improving thermal conductivity and shrinking the footprint versus conventional drain-down PQFN layouts. A power MOSFET is a voltage-controlled semiconductor switch that converts and regulates electrical energy by toggling between a low-resistance on state and a high-resistance off state. Within the broader taxonomy, this part is an N-channel enhancement-mode MOSFET, a sub-class of discrete power transistors, which sit under discrete semiconductors and ultimately under active components. MOSFETs are the workhorse of DC-DC conversion, motor drive and load switching across every voltage domain, with low-voltage OptiMOS 5 specifically targeting 12 V to 24 V rails in computing, telecom and automotive subsystems. Key features of this part include 30 V VDS max, 1.20 mOhm RDS(on) (typ, VGS=10 V), 34 A continuous drain current (Ta, 25 C) and 224 A pulsed drain current (Tc, 25 C, pulse duration per datasheet), 2.5 W power dissipation (Ta) and 107 W (Tc), with VGS(th) in the 1.0 V to 2.4 V range typical of OptiMOS 5 logic-level variants. The Source-Down PQFN 3.3x3.3 package with center-gate pinout improves power density, eases PCB layout symmetry, and reduces the source inductance loop area for cleaner switching at high di/dt. Architecture-wise the device combines a planar-style OptiMOS 5 cell array with the Source-Down flip-chip assembly, allowing the bottom thermal pad to carry source current directly to the PCB. This reduces package parasitic source inductance by approximately 50 percent compared to a drain-down part in the same footprint, lowering switching losses in hard-switched buck converters, half-bridges, and eFuse / hot-swap circuits where every milli-ohm of RDS(on) and every nanohenry of Ls translates directly into wasted energy and ringing. Typical applications include synchronous rectification in 12 V VRM and POL buck converters for servers, AI accelerator cards and high-current GPU power stages, hot-swap and OR-ing switches on 24 V telecom boards, motor drive H-bridges for low-voltage BLDC pumps and fans, USB-PD and high-current Type-C source controls, battery protection FETs in 1-3 s packs, and high-side load switches in industrial PLCs. The 3.3x3.3 mm footprint is intentionally small to fit space-constrained modules. When designing with the IQE012N03LM5CG, observe SOA derating carefully: continuous Ta rating of 34 A assumes a reference footprint (FR4 40x40x1.5 mm with 6 cm2 copper, per Infineon test conditions) and falls rapidly with rising ambient temperature. Use Kelvin-source pin 4 (KS) for gate drive return to avoid source-bond voltage drop modulating VGS. Match VGS drive to 10 V (logic-level compatible) for full RDS(on) achievement, and gate-drive peak current per the OptiMOS 5 typical application circuit. This page synthesizes Infineon distributor pricing as of 2026-09-14, same-package drop-in alternatives, comparison tables against competing 30 V N-FETs, and practical design notes beyond what the manufacturer datasheet alone surfaces for new design-in.
IQE012N03LM5CGSCATMA1 - 30V 1.15mΩ OptiMOS 5 MOSFET | Infineon
The Infineon IQE012N03LM5CGSCATMA1 is an N-channel OptiMOS 5 low-voltage power MOSFET rated at 30 V VDS with an ultra-low maximum on-resistance of 1.15 mΩ and a continuous drain current of 224 A (Tc), packaged in a 3.3 × 3.3 mm PQFN Source-Down dual-side cooled land grid (PG-WHTFN-9-1). The device is offered on Tape & Reel for high-volume SMT assembly. An N-channel power MOSFET is a voltage-controlled three-terminal switch in which a gate-source voltage (VGS) induces an inversion layer in the silicon channel, allowing current flow between drain and source. The OptiMOS 5 family is Infineon's fifth-generation 30V-300V trench MOSFET platform optimized for low RDS(on) × gate charge (Qg) figure-of-merit — a key indicator of switching and conduction efficiency. The Source-Down PQFN package flips the silicon die so that the source terminal (instead of the drain) faces the PCB, enabling direct PCB-side cooling and simpler paralleling. Key features include a maximum RDS(on) of 1.15 mΩ at VGS = 10 V, a continuous ID of 34 A (Ta) / 224 A (Tc), a pulsed avalanche rating defined on the datasheet, and an operating junction range of -55 °C to +175 °C. The 3.3 × 3.3 mm Source-Down PQFN footprint reduces loop inductance in buck and half-bridge topologies, which lowers voltage overshoot during switching transitions. The part is fully RoHS compliant and qualified to JEDEC moisture sensitivity Level 1. Typical applications include high-density DC-DC point-of-load converters in servers and telecom hardware, hot-swap and OR-ing circuits on 12 V rails, motor-drive half-bridges in e-mobility tools, and synchronous-rectifier stages in telecom rectifiers. The Source-Down package enables direct copper cooling on the bottom pad, a thermal pathway unavailable on conventional drain-down PQFN devices. When designing with this part, prioritize a large top-side PCB thermal copper area over the Source pad and minimize the high-current source-loop area to reduce parasitic inductance. The dual-side cooled variant permits thermal vias that pull heat into inner copper planes, supporting high continuous current without external heatsinking.
IQE013N04LM6ATMA1 - 40V 1.35mΩ OptiMOS N-FET, PQFN 3.3x3.3 | Infineon
The Infineon IQE013N04LM6ATMA1 is a 40 V N-channel OptiMOS power MOSFET in a Source-Down PQFN 3.3x3.3 mm package, featuring a typical on-resistance of 1.35 mΩ at 10 V VGS, continuous drain current of 31 A (Ta) / 205 A (Tc), and a maximum power dissipation of 107 W (Tc). Designed for high-current, low-voltage switching, this part uses Infineon's OptiMOS trench technology to deliver industry-leading RDS(on) per footprint and superior thermal performance through the Source-Down flip-chip die attach. An N-channel MOSFET is a voltage-controlled semiconductor switch whose drain-source channel is enhanced by a positive gate-source voltage; when used as a low-side or high-side switch it converts a logic-level PWM into efficient power delivery, sitting in the broader hierarchy of discrete semiconductors (transistor > FET > MOSFET > power MOSFET > trench MOSFET). The Source-Down architecture flips the die so the source pads contact the PCB top layer, maximizing copper utilisation for cooling and shrinking the thermal loop inductance for cleaner switching. Key features include 40 V VDS max, ±20 V VGS rating, ultra-low 1.35 mΩ RDS(on) at VGS=10 V, gate threshold of 2 V typical, integrated ESD protection, and a Source-Down leadless package that reduces footprint by roughly 50% versus D²PAK while doubling power density. The PQFN-8 layout exposes the drain through thermal vias under the package body, supporting junction-to-case thermal resistance down to 1.4 °C/W per the OptiMOS Source-Down datasheet family. The IQE013N04LM6 is built on OptiMOS 6 40 V trench technology with a stripe-cell layout that minimises on-resistance per die area and a monolithic gate clamp for ESD robustness. The Source-Down topology routes the high-current source return through the PCB's top-side copper flood rather than through bond wires, which both improves thermal conductivity and reduces source inductance for faster, cleaner switching edges. Typical applications include 24 V telecom point-of-load converters, synchronous rectification in SMPS, motor drive half-bridges, USB-PD and e-mobility battery protection, and OR-ing / hot-swap controllers in 12 V/24 V industrial bus systems. The wide SOA and high pulse-current capability also suit hot-swap and eFuse use cases. When laying out this part, place sufficient copper under and around the Source-Down pads (top layer flood plus thermal via array to internal planes) to keep the junction below 150 °C; ignore the Source-Down pad pattern and the device will overheat even at modest continuous load. Always check the avalanche energy rating (EAS) and dv/dt immunity from the manufacturer datasheet before applying unclamped inductive switching. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not collated in the manufacturer datasheet, giving a procurement-aware view of the part alongside the electrical and thermal engineering data.
IQE013N04LM6SCATMA1 - 40V 1.35mΩ OptiMOS Source-Down MOSFET | Infineon
The Infineon IQE013N04LM6SCATMA1 is a 40 V N-channel OptiMOS power MOSFET with 1.35 mΩ maximum R<sub>DS(on)</sub> at 10 V V<sub>GS</sub>, housed in an 8-pin PG-WHSON-8-1 (3.3 mm × 3.3 mm Source-Down PQFN) package with an exposed thermal pad. It is rated for 31 A continuous drain current at T<sub>A</sub> = 25 °C and 205 A pulsed at T<sub>C</sub> = 25 °C, with power dissipation of 2.5 W (Ta) and 107 W (Tc). An N-channel power MOSFET is a voltage-controlled majority-carrier device whose conduction loss is governed by R<sub>DS(on)</sub> and whose switching loss is set by the gate charge Q<sub>G</sub> and the drain-source capacitance. The OptiMOS Source-Down family places the source connection on the bottom of the die and on the PCB footprint, enabling double-sided cooling through the exposed pad and direct top-side PCB copper for the drain, which lowers thermal resistance and shrinks the required PCB area for a given R<sub>DS(on)</sub>. As a 40 V part the IQE013N04LM6 belongs to the low-voltage power MOSFET hierarchy: MOSFET → power MOSFET → N-channel enhancement mode → OptiMOS low-voltage family → Source-Down topology → semiconductor. Key features include ±20 V maximum gate-source rating, 41 nC total gate charge at 10 V V<sub>GS</sub>, 3800 pF output capacitance C<sub>oss</sub> at 20 V V<sub>DS</sub>, and a Source-Down leadless package that simplifies thermal management. According to the manufacturer datasheet the absolute maximum ratings are defined with case temperature held at 25 °C; derating is required for higher case temperatures as shown in the safe operating diagram. The Source-Down die architecture flips the conventional Source-on-bottom layout, allowing the drain tab to sit on the top thermal pad and the source to bond directly to the PCB. This reduces package parasitic source inductance and improves current spreading, which is critical for high di/dt switching transitions in synchronous rectification stages. Typical applications include 12 V-24 V server and telecom point-of-load conversion, synchronous rectification in SMPS, motor drives, eMobility auxiliary loads, and USB Power Delivery high-current rails. The combination of very low R<sub>DS(on)</sub> and Source-Down thermal architecture suits space-constrained designs that previously required D²PAK footprints. Designers should observe the ±20 V V<sub>GS</sub> limit, place the gate driver within 5 mm of the gate pad, and provide at least 50 mm² of top-side drain copper for a 100 °C/W θ<sub>JA</sub> target. The Source-Down footprint is NOT pin-compatible with traditional DFN-style PQFN footprints; verify the land pattern against the manufacturer PG-WHSON-8-1 recommendation before board rework. This page synthesizes distributor inventory, verified drop-in and functional alternatives, and practical Source-Down layout notes that complement the manufacturer datasheet rather than restate it.
IQE018N06NM6CGATMA1 - 60V 178A OptiMOS 6 N-MOSFET | Infineon
The Infineon IQE018N06NM6CGATMA1 is an N-channel OptiMOS 6 power MOSFET rated for 60 V drain-source voltage and 178 A continuous drain current at case temperature, housed in the surface-mount PG-TTFN-9-3 (also marketed as TOLL/TTFN) package. According to the Infineon OptiMOS 6 60V family datasheet, the device delivers up to 37% lower R_DS(on) and roughly 25% better figure-of-merit versus the previous OptiMOS 5 generation. A power MOSFET is a voltage-controlled three-terminal switch used to efficiently route or modulate current in power-conversion circuits. The OptiMOS 6 family sits in the broader power MOSFET taxonomy (planar/trench N-MOSFET -> power MOSFET -> discrete semiconductor) and is optimized for low-voltage, high-current synchronous rectification, motor drive, and hot-swap applications where conduction and switching losses both matter. Key features of the IQE018N06NM6CGATMA1 include a maximum on-resistance of 1.8 mΩ (typical, at V_GS = 10 V), a logic-level 3.3 V gate-threshold rating for direct MCU GPIO drive, and a 25 A continuous / 178 A pulsed current envelope that allows aggressive SOA headroom. The package supports 2.5 W at 25 °C ambient and 125 W at case temperature, with a small footprint suitable for high-density DC-DC converters and server/OR-ing stages. Internally, OptiMOS 6 uses Infineon's latest trench-cell geometry combined with a thin-wafer epitaxial process to slash both R_DS(on) x A and Q_g x R_DS(on) figures of merit. The result is a die that switches faster and conducts better at the same silicon area, enabling higher frequency converters with smaller magnetics and reduced total BOM cost. Typical applications include 48 V to point-of-load synchronous rectification in telecom and datacom equipment, hot-swap and OR-ing FETs in server power supplies, e-fuse and battery-protection blocks in 48 V mild-hybrid automotive systems, motor drive half-bridges in industrial robotics, and USB-PD / Type-C sink controllers requiring high-current, low-loss switching. When designing with this part, prioritize gate-drive strength (peak gate current > 1 A is recommended to fully exploit the fast edge rates), use a Kelvin-source connection where the PCB layout exposes one, and respect the linear-mode SOA when the device is used as a hot-swap current limiter rather than a saturated switch. This page synthesizes Infineon distributor pricing, drop-in OptiMOS 6 alternatives, and design guidance that goes beyond a re-statement of the datasheet front page, with sources cited throughout.
IQE018N06NM6SCATMA1 - 60V 1.8mΩ OptiMOS 6 N-MOSFET | Infineon
The Infineon IQE018N06NM6SCATMA1 is an N-channel OptiMOS 6 power MOSFET in a PG-WHSON-8-1 (5x6 mm) surface-mount package, rated 60 V VDS with a typical on-resistance of 1.8 mΩ at 10 V VGS. It delivers a continuous drain current of 25 A at 25 °C case (178 A at TC), making it one of the lowest-RDS(on) parts in the 60 V OptiMOS 6 family. What is an N-channel power MOSFET? An N-channel MOSFET is a four-terminal voltage-controlled switch (Gate, Drain, Source, Body) that conducts electrons when a positive gate-to-source voltage exceeds its threshold. Within the broader hierarchy, this device is a discrete semiconductor -> power MOSFET -> N-channel MOSFET -> silicon enhancement-mode part of Infineon's OptiMOS 6 family, optimized for low RDS(on) and high figure-of-merit (FOM = RDS(on) × Qg) for switching power-conversion applications. Key features include a 3.3 V typical gate threshold, very low total gate charge, and Soft-switching optimization per the Infineon OptiMOS 6 datasheet. The 2.5 W power dissipation at TA and 125 W at TC provide designers with generous thermal headroom for high-current rails. Compared to OptiMOS 5, the 60 V OptiMOS 6 family offers >37% lower RDS(on) and ~25% higher FOM (Qg × RDS(on)) per Infineon's family marketing claims. Architecture-wise, the IQE018N06NM6SC uses Infineon's latest trench-cell silicon process, balancing ultra-low on-resistance with reasonable switching performance. The PG-WHSON-8-1 package provides an exposed drain pad for superior thermal spreading, reducing thermal resistance and enabling compact high-current PCB layouts. Typical applications include 48 V eFuse / hot-swap circuits, OR-ing FETs in telecom and server power supplies, 12 V to 48 V DC-DC converter synchronous rectification, motor-drive H-bridges, and high-current automotive load switches. The 60 V rating also leaves adequate headroom for 48 V industrial and telecom bus architectures. When designing with this MOSFET, pay close attention to gate-drive voltage (10 V VGS recommended for full RDS(on) enhancement), PCB copper area for heatsinking, and SOA derating at high VDS / continuous ID. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
IQE020N04LM6CGATMA1 - 40V 2.0mΩ OptiMOS 6 MOSFET | Infineon
The Infineon IQE020N04LM6CGATMA1 is an N-channel OptiMOS 6 low-voltage power MOSFET rated at 40 V drain-source breakdown, with a typical on-state resistance (RDS(on)) of approximately 2.0 mΩ at 10 V VGS, housed in the source-down center-gate PQFN 3.3 × 3.3 package (PG-TTFN-9-3). According to the Infineon datasheet, it delivers 25 A continuous drain current at TA = 25 °C and up to 166 A at TC = 25 °C, with power dissipation of 2.5 W (TA) and 107 W (TC) on the recommended 40 × 40 × 1.5 mm epoxy FR4 PCB with 6 cm² copper. A power MOSFET is a voltage-controlled semiconductor switch used to efficiently route or modulate current in power-conversion and motor-drive circuits. As a member of the OptiMOS 6 family, the IQE020N04LM6CG belongs to a hierarchy of N-channel enhancement-mode MOSFETs that sit within Infineon's broader low-voltage power MOSFET portfolio, optimized for 25–40 V synchronous rectification, hot-swap, and battery-protection applications. Compared with older OptiMOS 5 generations, OptiMOS 6 reduces figure-of-merit (FOM = RDS(on) × Qg) and improves switching performance at high di/dt. The package is the key differentiating feature. The source-down, center-gate PQFN 3.3 × 3.3 layout places the thermal pad and source connection on the bottom of the package - the same side that mounts to the PCB. This construction provides a direct thermal path from the die to the board, lowering RthJA substantially versus conventional drain-down QFN packages. It also enables top-side cooling, dual-side cooling, and a simplified PCB layout where the source is the natural ground-return. Typical applications include 24 V brushless DC (BLDC) motor drives, e-fuse and hot-swap controllers, battery-management systems (BMS) for 1S–10S lithium packs, point-of-load (POL) synchronous buck converters, USB-PD power paths, and 48 V mild-hybrid DC-DC converters. With RDS(on) of ~2.0 mΩ at 10 V VGS, conduction loss at 20 A is roughly 0.8 W, making it suitable for high-current density designs. Design considerations include VGS(th) gate-drive requirements (10 V drive recommended for full RDS(on) rating), PCB layout to minimize source-inductance in the gate loop, and thermal management via copper area and via arrays. The exposed source-down pad should be soldered to a flooded copper pour for optimum heat spreading. This page consolidates distributor pricing, drop-in alternative listings, and practical layout guidance that goes beyond the manufacturer's datasheet to accelerate your design and sourcing decisions.
IQE020N04LM6CGSCATMA1 - 40V OptiMOS 6 2.0mΩ N-MOSFET, PG-WHTFN-9
The Infineon IQE020N04LM6CGSCATMA1 is an OptiMOS 6 single N-channel power MOSFET rated at 40 V VDS with a maximum on-resistance of approximately 2.0 mΩ (per part number decode IQE = 2.0 mΩ at 10 V VGS) and a continuous drain current of 25 A at TA = 25 °C rising to 166 A at TC = 25 °C, packaged in a 9-pin PG-WHTFN-9-1 Source-Down dual-side-cooled PQFN 3.3×3.3 mm surface-mount land pattern. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled three-terminal device whose channel conductance is modulated by an insulated gate electrode. Low-voltage N-channel power MOSFETs are the dominant synchronous-rectifier and buck-switch building blocks in switched-mode power supplies, where they sit in the broader hierarchy of power-management semiconductors that includes gate drivers, DC-DC controllers, and linear regulators. Source-Down dual-side-cooled packages like PG-WHTFN-9-1 flip the conventional source-drain layout so the source terminals contact the PCB thermal pad, allowing direct heat extraction from both top and bottom sides of the die. Key features include Infineon OptiMOS 6 trench technology, low figure-of-merit (RDS(on) × Qg) for high-frequency switching, integrated source-down symmetrical cooling for improved thermal performance, and an optimized gate-charge profile. Per the manufacturer datasheet, the part is qualified for 2.5 W power dissipation at TA = 25 °C and 107 W at TC = 25 °C on a reference 40 mm × 40 mm FR4 PCB with 6 cm² copper. Typical applications include synchronous rectification in 12 V-to-low-voltage buck converters, battery management system (BMS) protection and charging stages, USB Power Delivery (PD) load switches, hot-swap controllers, and high-current motor-drive low-side switches. The Source-Down thermal path reduces PCB temperature rise versus conventional DFN packages of the same footprint. When designing with this MOSFET, ensure the gate-drive voltage reaches at least 10 V for full enhancement and minimal RDS(on), and respect the SOA boundaries for pulsed loads. A thermally-optimized PCB layout with adequate via-array stitching under the exposed pad is mandatory to achieve the rated TC performance.
IQE022N06LM5CGATMA1 - 60V OptiMOS 5 N-Ch MOSFET, 2.2mΩ | Infineon
The Infineon IQE022N06LM5CGATMA1 is a 60V N-channel power MOSFET built on the OptiMOS 5 process technology, delivering an ultra-low typical R_DS(on) of 2.2 mΩ at 10V V_GS in a compact PG-TTFN-9-3 (PQFN 3.3x3.3) surface-mount package. The part is rated for 24A continuous drain current at T_A=25°C and 151A continuous at T_C=25°C, making it suitable for high-current DC-DC converter, motor drive, and OR-ing switch applications where both low conduction loss and small PCB footprint are mandatory. A power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled three-terminal semiconductor device in which the gate field modulates a conduction channel between drain and source. N-channel enhancement-mode MOSFETs like the IQE022N06LM5 are the workhorses of modern power electronics, sitting in the hierarchy: power MOSFET -> discrete semiconductor -> power switch -> power management IC. OptiMOS 5 is Infineon's fifth-generation 60V-300V power-MOSFET platform optimized for synchronous rectification and buck/boost topologies. Key features include 2.2 mΩ typical on-resistance at V_GS=10V, fast switching with optimized gate charge (Q_G), low Q_rr body-diode reverse recovery, and a 100W power dissipation rating at the case. The PQFN 3.3x3.3 mm package with an exposed top-side cooling structure offers an exceptionally low thermal resistance path, enabling 100W dissipation with a properly designed PCB land pattern. A logic-level gate drive is not required - the standard 10V gate drive delivers full enhancement. Architecturally, OptiMOS 5 uses Infineon's advanced trench-cell geometry that maximizes channel width per unit silicon area, shrinking R_DS(on) without raising C_iss or Q_G. This balance - low R_DS(on) together with modest gate charge - yields high efficiency in hard-switched 12V-48V buck converters and in 48V bus OR-ing circuits. The part also integrates a robust avalanche-rated body diode and is qualified for industrial temperature ranges. Typical applications include 48V telecom and server intermediate bus converters, synchronous rectification on the secondary side of isolated DC-DC modules, OR-ing FETs in redundant N+1 power shelves, motor-control H-bridges for 24V-48V BLDC drives, and USB-PD / e-Marked cable protection. The very low R_DS(on) keeps conduction loss minimal even at high continuous currents on small PCBs. When designing with this MOSFET, prioritize thermal copper pour under the exposed pad and minimize parasitic source-inductance in the gate-drive loop to avoid dv/dt-induced turn-on. For high-side use, verify that the bootstrap or gate-driver supply can deliver the Q_G charge at the target switching frequency without excessive ringing. This page synthesizes distributor pricing, drop-in alternatives, and practical thermal design notes that complement the manufacturer datasheet.
IQE022N06LM5CGSCATMA1 - 60V 151A OptiMOS 5 N-FET | Infineon
Infineon IQE022N06LM5CGSCATMA1 is an N-Channel 60V OptiMOS 5 power MOSFET delivering 151A continuous drain current at TC, 2.2 mOhm maximum on-resistance, and 100W power dissipation in the compact PG-WHTFN-9 (5x6mm) surface-mount package. The trench silicon process minimizes RDS(on) and figure-of-merit losses, making it ideal for high-current switching in space-constrained designs. It supports a 2.3V gate-threshold range and is designed for telecom, server, and 48V bus applications. What is an N-Channel MOSFET? An N-Channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled switch where current flows between drain and source when a positive gate-source voltage is applied above the threshold. Power MOSFETs like the OptiMOS 5 family sit in the hierarchy of discrete semiconductors -> transistors -> MOSFETs -> trench MOSFETs, where lower on-resistance translates directly into lower conduction losses and higher efficiency in switching regulators and motor drives. Key features include 2.2 mOhm maximum RDS(on) at VGS=10V, 60V drain-source breakdown voltage, 151A continuous drain current at TC (24A at Ta per DigiKey), and a 100W maximum power dissipation rating. The PG-WHTFN-9 package offers an exposed thermal pad for low thermal resistance, enabling sustained high-current operation. OptiMOS 5 technology provides superior switching performance with low gate charge, reducing driver losses in high-frequency applications. Technical depth: the device uses trench-gate architecture optimized for low figure-of-merit (FOM = RDS(on) x Qg). The result is a MOSFET capable of high-frequency switching (>500 kHz) without excessive driver losses. The PG-WHTFN-9 package's source-down configuration enables direct PCB heatsinking via copper pours. Typical applications include 48V telecom and server DC-DC converters, motor drives, synchronous rectification in SMPS, battery management systems, and load switching in industrial automation. The combination of low RDS(on) and high current rating suits point-of-load converters delivering >50A per phase. Design consideration: maintain VGS above 10V for full enhancement. Use a gate-driver with sufficient peak current (>1A) to charge the input capacitance quickly. PCB layout requires minimal source-loop inductance - place input capacitors directly across drain and source pads. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
IQE031N08LM6CGSCATMA1 - 80V OptiMOS 6 N-Ch MOSFET 127A | Infineon
The Infineon IQE031N08LM6CGSCATMA1 is an 80 V N-channel logic-level power MOSFET from the OptiMOS 6 40-100 V family, supplied in the 3.3 mm x 3.3 mm Source-Down Center-Gate (DSC) PQFN/WHTFN-9 package. It is rated for 18 A continuous drain current at 25 C ambient (Ta) and 127 A continuous drain current at case temperature (Tc), with power dissipation of 2.5 W (Ta) and 125 W (Tc). The device is qualified for synchronous rectification in computing and telecom power conversion stages, where its 80 V drain-to-source rating and 100% avalanche-tested trench cell provide the ruggedness required for SMPS topologies. A power MOSFET is a voltage-controlled three-terminal semiconductor switch used to commutate current in switching power supplies, motor drives, and load management circuits. Within the power-management hierarchy, a MOSFET sits below DC-DC converter and buck/boost controller ICs as the low-side or high-side synchronous switch. The OptiMOS 6 generation represents Infineon's latest 40 V to 100 V trench technology, designed to minimize conduction losses (RDS(on)) and switching losses (Qg, Qgd) simultaneously to maximize light-load and full-load efficiency in telecom 48 V and server 12 V rails. Key features include very low on-state resistance per die area, integrated gate protection against ESD, and logic-level gate drive compatibility (VGS(th) in the 1 V to 2.5 V region) that allows direct PWM drive from standard 3.3 V or 5 V controller outputs without an external gate-driver stage. The Source-Down package brings the source potential to the bottom thermal pad, doubling the effective cooling surface against the PCB copper pour and lowering thermal resistance junction-to-board. The Center-Gate pinout simplifies paralleling of multiple devices by equalizing gate-loop inductance. Typical applications include synchronous rectification on the secondary side of isolated DC-DC converters, hot-swap and OR-ing controllers on 48 V telecom boards, low-side switches in buck converters for server VRMs, and battery protection in 12 V/24 V e-mobility and industrial systems. The 80 V rating provides ample margin above 48 V nominal rails and supports transient 60 V surge conditions common in PoE and automotive 12 V systems. Designers should observe the drain-to-source avalanche rating and consult Diagram 2 in the manufacturer datasheet for thermal derating above 25 C. Because this is a Source-Down device, the PCB land pattern and thermal via array must be designed specifically for the WHTFN-9 DSC footprint - do not reuse a standard PQFN-9 land pattern. This page synthesizes Infineon distributor pricing, drop-in OptiMOS 6 cross-references, and Source-Down PCB layout guidance not aggregated on the manufacturer's product page.
IQE036N08NM6ATMA1 - 80V OptiMOS 6 N-MOSFET, 3.6mΩ | Infineon
The Infineon IQE036N08NM6ATMA1 is an 80V N-channel power MOSFET from the OptiMOS 6 family, featuring an ultra-low typical on-resistance of 3.6 mΩ and continuous drain current capability up to 118A at Tc, housed in the compact 3.3x3.3 mm PQFN Source-Down (PG-TSON-8-5) package. A power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled semiconductor switch used for switching and amplifying electronic signals in power conversion applications. It belongs to the broader category of discrete semiconductors, sitting within the power MOSFET family that itself is a subset of transistors. Power MOSFETs are fundamental building blocks in switch-mode power supplies (SMPS), motor drives, DC-DC converters, and battery protection circuits, where their low on-resistance minimizes conduction losses and high switching speed reduces switching losses. The IQE036N08NM6ATMA1 is rated for 80V drain-to-source voltage (VDS), with pulsed drain current up to several hundred amps and gate threshold voltage typically in the 1-3V range. Key technical features include low RDS(on) of 3.6 mΩ at VGS=10V, low gate charge (Qg) for fast switching, an integrated source-down configuration that improves thermal dissipation to the PCB, and avalanche-rated single-pulse capability. The Source-Down package places the source potential on the exposed pad, enabling direct top-side cooling. The OptiMOS 6 platform represents Infineon's latest-generation trench MOSFET technology, delivering a 30-40% RDS(on) improvement over the prior OptiMOS 5 generation in the same footprint. This enables higher power density designs, smaller magnetics, and cooler operation. The technology is qualified to JEDEC standards and supports harsh-environment industrial and automotive use cases. Typical applications include 48V e-fuse and hot-swap circuits in telecom and AI server power distribution, high-current synchronous rectification in isolated and non-isolated DC-DC converters, battery management system (BMS) protection in 48V mild-hybrid and battery-powered tools, USB Power Delivery (PD) sink/source switches, and motor drive half-bridges for e-bikes, drones, and small robotics. The combination of low RDS(on) and Source-Down thermal architecture suits these high-current-density use cases. Design consideration: ensure the gate drive voltage reaches at least 10V (VGS(th) typical 2V) for full enhancement; a dedicated gate driver IC (e.g. UCC27211) is recommended over a logic-level GPIO. Source-down layout requires placing thermal vias directly under the exposed pad to the inner power plane, and the gate return (Kelvin source connection) must be tied to the source pad rather than the power-source trace to avoid gate-bounce induced turn-on. This page synthesizes distributor pricing, parametric drop-in alternatives, and PCB layout design notes specific to the Source-Down PQFN 3.3x3.3 footprint that are not consolidated in the manufacturer datasheet.
IQE036N08NM6CGATMA1 - 80V 118A OptiMOS 6 N-MOSFET | Infineon
The Infineon IQE036N08NM6CGATMA1 is an 80 V, N-channel OptiMOS™ 6 power MOSFET with 3.6 mOhm typical Rds(on), rated for 118 A continuous drain current at Tc, packaged in a 3.3 x 3.3 mm Source-Down PQFN (PG-TTFN-9-3) land-grid array. It is engineered for high-current synchronous rectification, OR-ing, and motor-drive stages where minimum conduction loss per square millimeter of PCB area is the primary design constraint. A power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled switch used to efficiently route or modulate current in power-conversion and motor-drive circuits. The OptiMOS 6 family sits at the high-current, low-Rds(on) tier of Infineon's trench-FET portfolio, positioned as a key building block inside the broader power-management hierarchy of synchronous DC-DC converters, hot-swap controllers, and e-fuse stages. The Source-Down PQFN package places the thermal pad on the source side rather than the drain, allowing direct top-side cooling and very low package parasitic inductance. Key features of the IQE036N08NM6 include an industry-leading 3.6 mOhm maximum Rds(on) at 10 V Vgs, a logic-level friendly 1.0 V typical gate threshold, integrated ESD protection, and 100% Rg- and UIS-tested production. The Source-Down PG-TTFN-9-3 package reduces source inductance to under 1 nH and achieves a junction-to-case thermal resistance (RthJC) suitable for 125 W continuous dissipation when mounted on a properly sized copper land pattern with thermal vias to an internal plane. Architecturally, the device uses Infineon's latest OptiMOS 6 trench cell, which shrinks pitch to single-digit microns and replaces the conventional drain-down lead frame with a copper-clip Source-Down structure. The result is a roughly 30% lower Rds(on) per area versus the previous OptiMOS 5 generation, plus reduced ringing during hard switching because the high-current source loop is on the top metal layer directly above the die. Typical applications include 48 V server hot-swap and OR-ing FETs, telecom brick DC-DC converters, BLDC motor-drive half-bridges, battery protection FETs in power tools, and USB-PD/EPR high-current sink paths. The 80 V rating gives ample headroom above 48 V nominal buses and protects against transient spikes on 24 V industrial rails. When designing with this part, pay close attention to PCB layout: the Source-Down package requires a flooded top-side copper pour stitched with thermal vias directly under the source pad. Always check safe operating area (SOA) curves before paralleling multiple devices for load sharing. This page synthesizes distributor pricing, drop-in alternatives from the OptiMOS 6 family and competitor offerings, and practical layout/thermal notes not aggregated on a single manufacturer page.
IQE036N08NM6CGSCATMA1 - 80V 118A OptiMOS 6 N-MOSFET | Infineon
The Infineon IQE036N08NM6CGSCATMA1 is an 80 V N-channel power MOSFET from the OptiMOS 6 family, rated at 16.7 A continuous drain current at TA (ambient) and 118 A at TC (case), with 2.5 W power dissipation at TA and 125 W at TC, packaged in the surface-mount PG-WHTFN-9-1 (PQFN 3.3x3.3) Source Down Center Gate Dual-Side Cooling footprint. An N-channel power MOSFET is a voltage-controlled semiconductor switch that uses an insulated metal-oxide gate to control current flow between drain and source terminals. In the broader taxonomy, N-MOSFETs belong to the power MOSFET family, which sits within discrete semiconductors and ultimately within power management and switching conversion building blocks. OptiMOS 6 represents Infineon's latest trench-technology generation, optimised for switching-converter primary and synchronous-rectification stages where figure of merit (FOM = RDS(on) x Qg) directly determines converter efficiency. Key differentiating specifications include the 80 V drain-source breakdown voltage (VDS max), the dual-side cooling package that lowers thermal resistance by exposing the source die on the bottom side, and the central-gate pinout that simplifies PCB layout and parallel-device symmetry. The Source Down configuration flips the conventional drain-down arrangement, allowing heat to be extracted through both top and bottom PCB copper for high-current-density designs. The PG-WHTFN-9-1 (PQFN 3.3 x 3.3 mm) footprint uses a center-gate layout with Kelvin source sense and dual-side cooling to balance gate-drive loop symmetry against thermal performance. This architecture is targeted at telecom and server 48 V point-of-load converters, USB Power Delivery synchronous buck stages, motor-drive H-bridges, and hot-swap controllers where ultra-low RDS(on) and minimal parasitic inductance are mandatory. Typical applications include 48 V to 12 V intermediate bus converters in hyperscale data centres, e-mobility auxiliary power modules, synchronous rectification in telecom rectifier bricks, industrial buck/boost converters, and high-current USB-PD sinks/sources. Designers should review the SOA curves in the manufacturer datasheet before operating near the maximum 118 A TC rating, and ensure adequate PCB copper on both top and bottom layers to exploit the dual-side cooling benefit.
IQE050N08NM5CGATMA1 - 80V N-Ch MOSFET 5mΩ Source-Down | Infineon
The Infineon IQE050N08NM5CGATMA1 is an 80V N-channel MOSFET built on Infineon's Source-Down platform, featuring a maximum on-resistance of 5.0 mΩ and continuous drain current of 16A (Ta) or 101A (Tc), housed in a surface-mount PG-TTFN-9-1 package. The Source-Down architecture places the source potential on the package bottom pad, enabling direct PCB thermal coupling and simplified Kelvin-source layout for low gate-loop inductance. It is rated for 2.5W (Ta) and 100W (Tc) power dissipation and targets high-current switching in drives, servers, and telecom power stages. A power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled switch used to efficiently route or modulate current in power-conversion circuits. Within the broader taxonomy, the IQE050N08NM5CGATMA1 belongs to the discrete-semiconductor MOSFET family, specifically the N-channel enhancement-mode power MOSFET category used for low-side or high-side switching in DC-DC converters, motor drives, and hot-swap controllers. Source-Down technology is a recent packaging evolution that improves both thermal dissipation and gate-drive integrity versus traditional source-up DFN packages. Key features include a 5.0 mΩ maximum RDS(on) at VGS=10V, an 80V VDS rating that provides ample margin for 48V telecom and industrial bus rails, and Source-Down packaging that enables top-side cooling. The 9-pin PG-TTFN configuration integrates a large source tab on the package bottom, reducing both RθJA and parasitic source inductance during high-di/dt switching transitions. Gate threshold is tuned for standard 10V drive, simplifying compatibility with most gate-driver ICs. Technically, the device leverages Infineon's latest OptiMOS 5 80V silicon, which minimizes both conduction loss and switching loss. The combination of low Qg, low Qrr, and the Source-Down package geometry yields high efficiency in hard-switched topologies such as buck converters, half-bridges, and OR-ing switches. The optimized body diode supports use in synchronous-rectification roles with minimized reverse-recovery losses. Typical applications include 48V server and telecom point-of-load converters, motor-drive half-bridges in industrial automation, battery-management OR-ing and protection FETs in e-mobility, and high-current hot-swap controllers in networking equipment. Its low RDS(on) makes it well suited for high-current, low-duty-cycle switching stages where conduction loss dominates. When designing with this part, prioritize Kelvin-source connection to pin 9 (the dedicated gate-return) and use a wide copper pour under the bottom source pad to achieve the lowest thermal resistance. The 80V rating gives generous design margin in 48V systems, but the user must still observe the SOA curve for high-current pulsed conditions. This page synthesizes distributor pricing, pin-to-pin compatible drop-in alternatives from the same Source-Down family, and practical thermal/layout guidance that goes beyond the manufacturer datasheet summary.
IQE050N08NM5CGSCATMA1 - 80V 99A OptiMOS 5 N-Channel MOSFET | Infineon
The Infineon IQE050N08NM5CGSCATMA1 is an N-channel enhancement-mode power MOSFET from the OptiMOS 5 80 V family, rated for 80 V VDS and continuous drain current up to 99 A (Tc) or 16 A (Ta), with a maximum on-resistance of 5.0 mOhm at 10 V VGS, housed in the surface-mount PG-WHTFN-9-1 Source-Down package. It is built on Infineon's latest 80 V OptiMOS 5 trench process, offering a 30% reduction in RDS(on) versus the prior OptiMOS generation and superior thermal performance thanks to the Source-Down leadframe that places the thermal pad on the source side instead of the drain side, allowing direct PCB cooling through the top-side copper. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled three-terminal semiconductor switch that uses an insulated gate to modulate the drain-source current. MOSFETs belong to the broader power-management discrete family, sitting in the hierarchy: power MOSFET -> discrete semiconductor -> semiconductor. OptiMOS is Infineon's brand name for its high-performance trench MOSFET families, and the Source-Down package is a specific leadframe variant in which the source is exposed at the bottom for direct PCB cooling. Key features of the IQE050N08NM5CGSCATMA1 include an industry-leading 5.0 mOhm RDS(on) at VGS=10 V, a logic-level compatible 3.8 V typical gate threshold, low gate charge Qg for high-frequency switching, and an integrated monolithic Schottky-like body diode with low Qrr for reduced switching losses in hard-switched topologies. The PG-WHTFN-9-1 package is a 9-pin surface-mount outline measuring 5 mm x 6 mm with a large exposed thermal pad. Typical applications include high-current synchronous rectification in server and telecom SMPS, motor drive half-bridges for industrial drives, hot-swap and OR-ing controllers in 48 V distribution, and high-efficiency DC-DC conversion stages where Source-Down cooling enables double-sided PCB layouts. Designers choose this part when low conduction loss and superior top-side cooling are required in a small SMD footprint. When designing with this part, place the Source-Down exposed pad on a top-side copper pour with thermal vias to inner planes, and ensure the drain traces (which are now on the bottom of the package) are routed as wide as possible. Gate-drive design should target 10 V VGS for lowest RDS(on); at 4.5 V the RDS(on) increases roughly 50% and conduction loss grows accordingly. This page synthesizes distributor pricing, drop-in alternatives from the Infineon OptiMOS 5 family and verified cross-brand equivalents, and practical design notes not found in the manufacturer datasheet.
IQE065N10NM5CGSCATMA1 - 100V 6.5mOhm N-Ch MOSFET | Infineon
The Infineon IQE065N10NM5CGSCATMA1 is a 100V N-channel power MOSFET built on Infineon's OptiMOS 5 technology, featuring an ultra-low on-resistance of 6.5 mOhm and rated for 85A continuous drain current at 25 C case temperature, housed in a Source-Down PG-WHTFN-9-1 surface-mount package. The Source-Down architecture places the die on the source potential, allowing direct cooling through the PCB top side and enabling a 3x improvement in thermal resistance versus conventional bottom-cooled DFN packages of similar footprint. A power MOSFET is a voltage-controlled semiconductor switch used to efficiently route or interrupt current in power-conversion circuits such as DC-DC converters, motor drives, and load switches. The MOSFET belongs to the discrete semiconductor family, sitting at the boundary between power management ICs (which integrate control) and passive components (which store or filter). The key figures of merit are on-resistance (RDS(on), affecting conduction loss), gate charge (Qg, affecting switching loss), and thermal resistance (RthJA, determining power-handling capability). Lower RDS(on) and lower Qg reduce both conduction and switching losses, raising system efficiency. Key features include 6.5 mOhm maximum RDS(on) at VGS=10V, a 100V VDS breakdown rating, 13A continuous drain current at ambient (85A at TC=25 C), and a power dissipation of 2.5W at TA or 100W at TC. The Source-Down PG-WHTFN-9-1 package delivers top-side cooling and a compact 3.3 mm x 3.3 mm footprint. The device also provides low gate charge for fast switching, an avalanche-rated body diode for inductive loads, and is lead-free and RoHS compliant. The OptiMOS 5 process uses a trench-gate structure that minimizes cell pitch and reduces both RDS(on) and Qg, with a Figure of Merit (FOM = RDS(on) x Qg) optimized for high-frequency switching. The Source-Down configuration eliminates the traditional source-wire bonds, reducing parasitic inductance and improving both thermal and electrical performance in synchronous-rectification and hot-swap topologies. Typical applications include server and telecom buck converters, brushless DC (BLDC) motor drives, industrial 48V e-fuse and hot-swap controllers, synchronous rectification in telecom isolated DC-DC modules, and high-current load switches in 24V-60V industrial buses. The wide safety margin between 100V rating and 48V/60V buses provides strong derating headroom for industrial reliability targets. When designing with this MOSFET, ensure the gate-driver voltage reaches at least 10V to achieve the specified 6.5 mOhm on-resistance; lower VGS dramatically increases conduction loss. The Source-Down pad must be soldered to a copper pour on the top PCB layer with multiple thermal vias to the inner ground plane, since the top side is the primary heat-extraction path. Always check the SOA curve in the manufacturer datasheet for transient conditions such as motor inrush or hot-swap events. This page synthesizes distributor pricing, drop-in alternatives from Infineon's OptiMOS 5 family, and practical Source-Down PCB layout guidance not consolidated in the manufacturer datasheet.
IQE220N15NM5ATMA1 - 150V N-Ch OptiMOS 5 MOSFET | Infineon
The Infineon IQE220N15NM5ATMA1 is an N-channel 150 V OptiMOS 5 power MOSFET in a Source-Down PG-TSON-8-5 package, delivering 22 mΩ RDS(on) at 10 V VGS and continuous drain current of 7 A (Ta) or 44 A (Tc), with a power dissipation rating of 2.5 W (Ta) and 100 W (Tc). An N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled, majority-carrier device whose drain-source conduction is gated by a positive threshold voltage on the gate. The OptiMOS 5 family represents Infineon's fifth-generation trench MOSFET platform, positioned within the broader power management IC and discrete semiconductor hierarchy as a building block for synchronous rectification, hot-swap, and high-frequency switching stages in modern power electronics. Key features include 150 V VDS max rating, 22 mΩ on-resistance (VGS = 10 V), 14.4 nC total gate charge, 14 pF Ciss, 340 pF Coss, 4.6 V VGS(th) at 46 µA, and an integrated Source-Down package that exposes the source lead to the top pad for improved thermal dissipation. The Source-Down PG-TSON-8-5 layout flips the conventional land pattern to deliver the thermal pad directly to the PCB's heat-spreading copper pours, lowering junction-to-ambient thermal resistance compared to standard TSON-8 outlines. Architecturally, the device uses Infineon's latest trench-cell process with a stripe-cell pitch optimized for low FOM (RDS(on) × Qg), enabling 100 kHz+ hard-switching operation in telecom and SMPS applications. The Source-Down leadframe routes the source terminal through the bottom of the die, allowing paralleled devices to share a continuous top-side copper plane as both electrical return and heatsink. Typical applications include 48 V telecom point-of-load converters, synchronous rectification in SMPS, hot-swap controllers on 80 V-100 V distribution rails, motor drive half-bridges, eFuse/ORing switches, and industrial e-mobility auxiliary converters. Compared to a standard MOSFET, the Source-Down variant shifts the system-level thermal budget toward the PCB rather than the package, simplifying mechanical design in space-constrained modules. When designing, place at least 100 mm² of top-side copper on the source pad, gate-drive the MOSFET from a 10 V capable driver with sub-50 ns rise/fall times, and respect the SOA at high drain voltages where thermal derating becomes critical. Validate VGS(th) at the minimum operating temperature to ensure full enhancement. This page synthesizes Infineon datasheet specifications, distributor pricing, drop-in alternatives, and Source-Down PCB layout guidance not found in standard MOSFET comparison tools.
IQE220N15NM5CGATMA1 - 150V 44A N-Ch OptiMOS 5 MOSFET | Infineon
The Infineon IQE220N15NM5CGATMA1 is an N-channel OptiMOS 5 power MOSFET rated at 150 V drain-to-source voltage with a continuous drain current of 44 A (at Tc) and on-state resistance of approximately 22 mOhm. Housed in a Source-Down PG-TTFN-9-3 surface-mount package, this device is engineered to deliver ultra-low conduction and switching losses for high-frequency power-conversion stages. An N-channel MOSFET (metal-oxide-semiconductor field-effect transistor) is a voltage-controlled majority-carrier device in which a positive gate-to-source voltage inverts an n-type channel and permits electron flow from drain to source. In the power-management taxonomy, this part belongs to the discrete MOSFET family, which sits under power semiconductors, used for switching and synchronous-rectification roles in SMPS, motor drives, and server/telecom power rails. Key features include 22 mOhm maximum RDS(on), a Source-Down package topology that pulls the source potential to the top side for superior thermal dissipation and simplified PCB layout, and 100 W continuous power dissipation at the case. The TTFN-9 footprint also features a large exposed drain pad that enables direct PCB heat-sinking with minimal thermal resistance. Gate threshold is optimized for standard 10 V drive. The device is built on Infineon's OptiMOS 5 trench process, which reduces gate charge (Qg) and output capacitance (Coss) compared with prior generations, thereby cutting switching-related losses at high frequency. The Source-Down arrangement lowers package parasitic source inductance and improves current-handling symmetry between paralleled MOSFETs, an important consideration for high-current multiphase converters. Typical applications include primary-side switches in telecom and server SMPS, synchronous-rectification MOSFETs in 48 V DC-DC converters, half-bridge stages in industrial motor drives, and hot-swap controllers in 12 V / 24 V distributed-power architectures. The 150 V rating provides ample margin above 100 V continuous input rails, improving reliability during transient spikes. When designing with this part, place the Source-Down source pad on the top copper layer with multiple thermal vias to inner copper planes to maximize heat extraction. Use a low-inductance gate-drive loop and a Kelvin-source connection where the package permits to prevent dynamic RDS(on) degradation. This page synthesizes distributor pricing, drop-in alternatives, and design notes not found in the manufacturer datasheet.
IQE220N15NM5CGSCATMA1 - 150V 44A OptiMOS 5 N-MOSFET | Infineon
The Infineon IQE220N15NM5CGSCATMA1 is an N-channel OptiMOS 5 power MOSFET rated at 150 V drain-source voltage and 44 A continuous drain current (at Tc), housed in a surface-mount PG-WHTFN-9 package with Source-Down technology. It features a maximum on-resistance of 22 milliohms and a 4.6 V gate threshold, dissipating 2.5 W at Ta or 100 W at Tc. The part is qualified for drives, SMPS, and telecom power-conversion applications. An N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled semiconductor switch in which a positive gate-source voltage creates a conducting channel between drain and source. It belongs to the broader hierarchy of discrete semiconductors -> transistors -> MOSFETs -> power MOSFETs -> power management components. N-channel variants offer lower on-resistance per unit silicon area than P-channel, making them preferred for high-current switching applications such as synchronous rectifiers and buck converter low-side switches. The IQE220N15NM5 leverages Infineon's OptiMOS 5 process technology, which delivers a 22 milliohm RDS(on) and Source-Down package construction that connects the source lead directly to the PCB copper, enabling superior thermal dissipation without an external heatsink. Compared to older OptiMOS generations, this part offers lower gate charge, faster switching, and improved figure-of-merit for high-frequency SMPS designs. The Source-Down orientation also simplifies PCB thermal layout by moving the drain potential to the top thermal pad area. Typical applications include motor drives for industrial automation, telecom 48 V buck converters, server and datacom point-of-load regulators, and synchronous rectification in telecom rectifiers. The 150 V rating provides substantial headroom above nominal 48 V and 80 V telecom bus rails, supporting high-efficiency step-down conversion in compact surface-mount designs where the Source-Down package replaces traditional D2PAK thermal solutions. A key design consideration is thermal management: at 44 A continuous current and 22 milliohm RDS(on), conduction loss alone reaches approximately 43 W at full load, requiring the Source-Down thermal pad to be soldered to a substantial copper pour on the PCB. The 4.6 V gate threshold means standard 10 V gate-drive is well within the safe operating range, but logic-level 5 V drive is not recommended for full enhancement. This page synthesizes distributor pricing, drop-in alternative analysis, and practical PCB layout guidance beyond the manufacturer datasheet.
IQE220N15NM5SCATMA1 - 150V 44A OptiMOS 5 Source-Down N-MOSFET | Infineon
The Infineon IQE220N15NM5SCATMA1 is an N-channel power MOSFET built on Infineon's OptiMOS 5 150 V platform with the proprietary Source-Down package technology. It delivers a typical on-state resistance of 22 mOhm at VGS=10 V, supports continuous drain current up to 44 A at Tc and 7 A at Ta, and is rated for 150 V VDS in a compact PG-WHSON-8-1 surface-mount package. The Source-Down construction flips the silicon die so the source connects to the exposed pad, which doubles the thermal dissipation area and lowers parasitic source inductance for cleaner switching. A power MOSFET is a voltage-controlled semiconductor switch used to efficiently route or modulate current in switching power supplies, motor drives, and load-management circuits. Within the broader power-management hierarchy, MOSFETs sit beneath voltage regulators and gate drivers as the active switching element; the OptiMOS 5 family from Infineon specifically targets high-frequency, high-efficiency DC-DC conversion by minimizing Figure-of-Merit (RDS(on) x Qg) to reduce both conduction and switching losses. Key features include a logic-level compatible VGS(th) of approximately 1.7 V (typical), low gate charge Qg in the tens of nC range, and an avalanche-rated single-pulse body diode. The PG-WHSON-8-1 Source-Down package offers dual-side cooling capability - the drain tab on top and source tab on bottom can both be soldered to copper pours, achieving a junction-to-case thermal resistance roughly half that of conventional DFN packages. The device is rated for 100 W power dissipation at Tc=25 C. Typical applications include 48 V telecom and server point-of-load converters, synchronous rectification in telecom SMPS, brushless DC motor drives, hot-swap and e-fuse circuits, and battery protection in power tools. The 150 V rating also makes it a strong candidate for industrial 24 V/36 V bus systems and solar micro-inverters. The Source-Down layout reduces PCB hot spots, enabling higher continuous current from a smaller footprint than legacy DPAK or SO-8 alternatives. When designing with this MOSFET, ensure the gate drive reaches at least 10 V for full RDS(on) enhancement, and place the gate-driver loop within 5 mm of the gate pin to minimize ringing. The Source-Down source tab must be soldered to a sufficient copper pour (typically 1 square inch minimum) to achieve the rated 100 W thermal envelope; without it, the device will derate severely above 2-3 W dissipation. This page synthesizes distributor pricing, drop-in alternatives, and design guidance beyond the manufacturer datasheet.