2ED21064S06JXUMA1 vs 1EDI20I12MFXUMA1 对比
详细并排对比 2ED21064S06JXUMA1 出自 Infineon 和 1EDI20I12MFXUMA1 出自 Infineon。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | 2ED21064S06JXUMA1 | 1EDI20I12MFXUMA1 |
|---|---|---|
| 品牌 | Infineon | Infineon |
| 分类 | Power MOSFET Drivers | Power MOSFET Drivers |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.85 | $1.84 |
| 功能 | High-Side and Low-Side Gate Driver | Isolated single-channel high-side gate driver |
| Configuration | Half-Bridge (2 outputs, non-inverting) | — |
| 拓扑 | High-Side, Low-Side with integrated bootstrap diode | — |
| Maximum Offset / Boot Voltage | 650 V | — |
| Supply Voltage (VCC) | 10 V to 20 V | — |
| Source Current (typical) | 0.29 A | — |
| Sink Current (typical) | 0.7 A | — |
| Rise Time (typical) | [DATA_NEEDED: rise time] | — |
| Fall Time (typical) | [DATA_NEEDED: fall time] | — |
| Propagation Delay (typical) | 100 ns | — |
| Channel-to-Channel Delay Match | [DATA_NEEDED: channel-to-channel delay match] | — |
| Under-Voltage Lockout | Yes (both channels) | — |
| Bootstrap Diode | Integrated | — |
| Input Logic Compatibility | 3.3 V / 5 V CMOS | — |
| 工作温度 | -40C to +125C | [DATA_NEEDED: operating temperature range] |
| 封装 | PG-DSO-14 (14-pin SOIC) | PG-DSO-8-51 (8-pin DSO, 4 mm creepage) |
| 安装类型 | Surface Mount | Surface Mount |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| RoHS 状态 | ROHS3 Compliant | Compliant |
| Negative Gate Drive Robustness | -0.7 V | — |
| Isolation Type | — | Galvanic (coreless transformer) |
| Number of Channels | — | 1 |
| Output Current (Source/Sink) | — | 2 A peak |
| Active Miller Clamp Current | — | 2 A |
| Maximum Operating Voltage (Switch side) | — | 1200 V |
| Propagation Delay (typ.) | — | 300 ns |
| Input Logic | — | Inverting / Non-inverting |
| 输出配置 | — | Single high-side driver |
| Minimum Creepage | — | 4 mm |
| Short Circuit Protection | — | Yes (clamping) |
| Supply Voltage (Secondary) | — | [DATA_NEEDED: secondary supply voltage range] |
| CMTI | — | [DATA_NEEDED: common-mode transient immunity] |
| UVLO | — | Yes (secondary side) |