5M160ZE64I5N vs 5M240ZT100I5N 对比

详细并排对比 5M160ZE64I5N 出自 Intel 和 5M240ZT100I5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 5M160ZE64I5N 5M240ZT100I5N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $4.13 $4.81
Device Family MAX V —
Logic Elements (LEs) 160 —
Macrocells 128 192
Maximum User I/O Pins 79 —
Pin-to-Pin Logic Delay (tPD) 7.5 ns —
User Flash Memory 4.0 Kbits 8 Kbit
Logic Array Blocks (LABs) 4 —
Supply Voltage - Core 3.3 V or 2.5 V —
I/O Bank Voltages 1.5 V / 1.8 V / 2.5 V / 3.3 V —
工作温度 -40C to +100C (Industrial) -40 C to +100 C (Industrial)
封装 64-pin EQFP (Exposed Pad) —
安装类型 Surface Mount Surface Mount
JTAG Support Yes (IEEE 1149.1, TMS/TDI/TDO/TCK) —
Differential I/O LVDS, RSDS, mini-LVDS, LVPECL (emulated) —
Configuration Non-volatile on-chip flash, instant-on —
RoHS 状态 Compliant —
Family — MAX V
Series — 5M240Z
Device Type — CPLD (Complex Programmable Logic Device)
Logic Elements — 240
Maximum User I/O — 114
User I/O Pins (per datasheet) — 79
引脚数 — 100
Package Type — TQFP-100 (T100)
Package Body Size — 14 x 14 mm
Lead Pitch — 0.50 mm
Core Voltage (VCCINT) — 1.8 V
I/O Bank Voltage (VCCIO) — 1.2 V to 3.3 V (bank-dependent)
Speed Grade — -5
Maximum Internal Frequency — 118.3 MHz
Pin-to-Pin Delay (tPD1) — 7.5 ns (per datasheet header)
Programming Interface — JTAG (IEEE 1149.1) / ISP
Configuration Memory — Non-volatile flash (instant-on)
Lead-Free / RoHS — Yes (LEAD FREE per datasheet header)
MSL 等级 — [DATA_NEEDED: MSL Level]
AEC-Q100 Automotive — Not qualified (Industrial grade)

数据手册与资源

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