5M240ZT100I5N vs 5M80ZT100I5N 对比

详细并排对比 5M240ZT100I5N 出自 Altera 和 5M80ZT100I5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 5M240ZT100I5N 5M80ZT100I5N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $4.81 $7.37
Family MAX V MAX V CPLD
Series 5M240Z —
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements 240 —
Macrocells 192 —
User Flash Memory 8 Kbit —
Maximum User I/O 114 —
User I/O Pins (per datasheet) 79 —
引脚数 100 —
Package Type TQFP-100 (T100) —
Package Body Size 14 x 14 mm —
Lead Pitch 0.50 mm —
Core Voltage (VCCINT) 1.8 V —
I/O Bank Voltage (VCCIO) 1.2 V to 3.3 V (bank-dependent) —
Speed Grade -5 —
Maximum Internal Frequency 118.3 MHz —
Pin-to-Pin Delay (tPD1) 7.5 ns (per datasheet header) —
工作温度 -40 C to +100 C (Industrial) —
Programming Interface JTAG (IEEE 1149.1) / ISP —
Configuration Memory Non-volatile flash (instant-on) Internal non-volatile flash (instant-on)
安装类型 Surface Mount Surface Mount
Lead-Free / RoHS Yes (LEAD FREE per datasheet header) —
MSL 等级 [DATA_NEEDED: MSL Level] MSL3 (per JEDEC J-STD-020)
AEC-Q100 Automotive Not qualified (Industrial grade) —
Logic Elements (LE) — 80
Macrocells (approx.) — 160
User I/O Pins — 64
封装 — TQFP-100 (100 pins, 0.5 mm pitch)
Pin-to-Pin Logic Delay (tPD) — 7.5 ns
Core Supply Voltage (VCCINT) — 1.71 V to 1.89 V (1.8 V typical)
I/O Supply Voltage (VCCIO) — 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V
Operating Temperature (Industrial) — -40 °C to +100 °C
UFM (User Flash Memory) — Up to 8 Kbits user-accessible
JTAG / ISP — IEEE 1149.1 boundary-scan + in-system programming
RoHS 状态 — Compliant

数据手册与资源

浏览全部产品 创建 BOM 获取报价