5M570ZM100C5N vs 5M570ZM100C4N 对比

详细并排对比 5M570ZM100C5N 出自 Altera 和 5M570ZM100C4N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 5M570ZM100C5N 5M570ZM100C4N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $6.80 $8.74
Product Family MAX V CPLD —
Series 5M570Z 5M570Z
Logic Elements / Macro Cells 440 —
Maximum User I/O Pins 74 —
Maximum Operating Frequency (fMAX) 118.3 MHz —
Pin-to-Pin Logic Delay (tPD) 9 ns (typical, per datasheet) —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
User Flash Memory (UFM) 8 Kbits —
Configuration Memory Type Non-volatile Flash —
封装 100-ball MBGA (Micro FineLine BGA), 0.5 mm pitch 100-ball MBGA (Micro BGA), tray
工作温度 0C to +85C (commercial) 0 C to +85 C (commercial)
JTAG Support IEEE 1149.1 boundary-scan + ISP —
Programming Interface JTAG / In-System Programming (Quartus II / Quartus Prime) JTAG (IEEE 1149.1), in-system programmable
RoHS 状态 Compliant Compliant
安装类型 Surface Mount (BGA) Surface Mount
Family — MAX V
Macro Cells — 440
Logic Elements (LEs) — 440
Maximum Internal Frequency — 184.1 MHz
Pin-to-Pin Delay (tPD) — 9.0 ns
Core Voltage — 1.8 V
Configuration Memory — Non-volatile flash, instant-on
User Flash Memory — Yes (8 Kbits)
Programmable I/O Pins — [DATA_NEEDED: I/O pin count for M100 package]
I/O Standards — LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V, PCI
Lead-Free — Yes

数据手册与资源

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