CDK1307CILP40 vs CDK2307CILP64 对比

详细并排对比 CDK1307CILP40 出自 MaxLinear 和 CDK2307CILP64 出自 MaxLinear。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

MaxLinear
CDK1307CILP40 CDK1307CILP40 - 12/13-bit 65MSPS Ultra-Low Power ADC | Exar

CDK1307CILP40 - 12/13-bit 65MSPS Ultra-Low Power ADC | Exar

CDK1307CILP40 ✓ 量产中
MaxLinear
CDK2307CILP64 CDK2307CILP64 - Dual 65MSPS 12/13-bit ADC | MaxLinear

CDK2307CILP64 - Dual 65MSPS 12/13-bit ADC | MaxLinear

CDK2307CILP64 ✓ 量产中

规格对比

参数 CDK1307CILP40 CDK2307CILP64
品牌 MaxLinear MaxLinear
分类 ADC/DAC ADC/DAC
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $3.95 $5.41
Part Number CDK1307CILP40 CDK2307CILP64
Manufacturer MaxLinear (formerly Exar/Cadeka) MaxLinear (formerly Exar / Cadeka)
功能 Analog-to-Digital Converter (ADC) Dual-channel Analog-to-Digital Converter (ADC)
分辨率 12-bit / 13-bit selectable 12-bit / 13-bit
Sample Rate 65 MSPS (family supports 20/40/65/80 MSPS) —
Architecture Multi-stage pipeline with digital error correction —
Input Type Single-ended analog input Differential analog inputs
Full-Scale Input Range 1 Vpp typical —
Supply Voltage (Analog) 3.3 V —
Supply Voltage (Digital) 3.3 V —
Reference Internal (1.2 V bandgap) —
Output Interface Parallel CMOS —
Control Interface CMOS serial configuration —
封装 40-pin LQFP (LP) 64-pin QFN (LP64) with exposed pad
工作温度 -40 C to +85 C (industrial) —
RoHS 状态 Compliant [DATA_NEEDED: RoHS status]
Number of Channels — 2
Maximum Sample Rate — 80 MSPS (12-bit), 65 MSPS (13-bit)
Supported Sample Rates — 20 / 40 / 65 / 80 MSPS
Converter Architecture — Pipelined with digital error correction
Digital Output — Parallel CMOS
Data Interface — CMOS parallel
Reference Type — Internal (on-chip)
安装类型 — Surface Mount
Packaging — Tray
工作温度范围 — [DATA_NEEDED: operating temperature range]

数据手册与资源

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