CDK2307CILP64 - Dual 65MSPS 12/13-bit ADC | MaxLinear
料号： CDK2307CILP64 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.42 | $8.42 |
| 10 | $7.51 | $75.10 |
| 100 | $6.62 | $662.00 |
| 500 | $5.99 | $2,995.00 |
| 1,000 | $5.41 | $5,410.00 |
CDK2307CILP64 概述
An ADC (Analog-to-Digital Converter) is a data acquisition component that converts real-world analog signals into discrete digital codes for downstream processing by FPGAs, DSPs, microcontrollers, or ASICs. Within the converter hierarchy, the CDK2307CILP64 sits in the pipelined-ADC subcategory, which is the dominant topology for sampling rates between 10 MSPS and 250 MSPS because it balances high input bandwidth and resolution against modest die area and power. Selection between SAR (successive-approximation) and pipelined ADC families is driven primarily by the required sample rate and channel count.
Key features include simultaneous dual-channel sampling at up to 80 MSPS, a maximum sample rate of 80 MSPS at 12 bits and 65 MSPS at 13 bits, CMOS-compatible digital I/O, and an internal voltage reference that eliminates external reference components. The wide input common-mode range and low differential nonlinearity (DNL) make the converter well-suited to intermediate-frequency (IF) sampling, multi-carrier base-station receivers, and high-density video / imaging front ends. Power dissipation scales linearly with sample rate, allowing designers to trade speed for power in lower-throughput operating modes.
Architecturally, each channel of the CDK2307CILP64 uses a multi-stage pipelined switched-capacitor core followed by digital error-correction logic. The internal reference and clock-receiver blocks are shared between channels, while the analog inputs and digital outputs are independent, allowing simultaneous sampling of two real signals or one I/Q complex signal pair in a baseband or low-IF radio chain.
Typical applications include wireless infrastructure (GSM/EDGE/UMTS base-station receiver IF stages), cable-modem / set-top box downstream digitizers, multi-channel test and measurement instruments, ultrasound beamforming front ends, and dual-channel imaging / video capture. The 64-pin QFN exposed-pad package supports surface-mount PCB assembly and provides a low-thermal-resistance path to the PCB copper for heat spreading during sustained high-sample-rate operation.
When designing with this part, ensure each analog input is driven from a low-impedance, wideband differential buffer; bandwidth-limiting the analog front end below the Nyquist frequency (half the sample rate) prevents aliasing but must not degrade the aperture-time accuracy. Decouple AVDD and DVDD pins separately at the IC with 100 nF ceramic capacitors to keep the high-frequency switching currents out of the analog ground return.
This page synthesizes distributor pricing, parametric comparisons against pin-compatible dual ADCs, and practical PCB-layout guidance that goes beyond what is found in the manufacturer datasheet PDF.
直接替换替代料： CDK2307CILP64 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CDK2307CILP64 （相同外形与封装尺寸） ——差异在于 Package, Resolution, Input Type, Manufacturer, Number of Channels.
快速对比工具——选择替代料号进行并排对比：
CDK2307CILP40
✅ 直接替换📋 参考替代料（不在目录中）
CDK1307CILP40
✅ 直接替换✓ 有现货
$3.95 / 个
查看数据手册 →CDK2307CILP64 最大额定值与电气特性
| Manufacturer | MaxLinear (formerly Exar / Cadeka) |
| Part Number | CDK2307CILP64 |
| 功能 | Dual-channel Analog-to-Digital Converter (ADC) |
| Number of Channels | 2 |
| 分辨率 | 12-bit / 13-bit |
| Maximum Sample Rate | 80 MSPS (12-bit), 65 MSPS (13-bit) |
| Supported Sample Rates | 20 / 40 / 65 / 80 MSPS |
| Converter Architecture | Pipelined with digital error correction |
| Input Type | Differential analog inputs |
| Digital Output | Parallel CMOS |
| Data Interface | CMOS parallel |
| Reference Type | Internal (on-chip) |
| 封装 | 64-pin QFN (LP64) with exposed pad |
| 安装类型 | Surface Mount |
| Packaging | Tray |
CDK2307CILP64 64-pin qfn (lp64) with exposed pad 引脚配置指南
CDK2307CILP64（64-pin qfn (lp64) with exposed pad 封装）的引脚配置。 该模拟元件具有输入、输出和电源引脚。请参阅制造商数据手册以了解失调调零、补偿和使能引脚配置。适用于信号调理和放大器电路。
暂无详细引脚数据： CDK2307CILP64.
请参阅 数据手册 以查看完整引脚配置。
典型应用
CDK2307CILP64 适用于 6 应用s: Wireless Infrastructure Base Station IF Sampling, Dual-Channel Video and Imaging Digitizer, Cable Modem and Set-Top Box Downstream Receiver, Multi-Channel Test and Measurement Instrumentation, Ultrasound Beamforming Front End, Software-Defined Radio I/Q Digitizer.
Wireless Infrastructure Base Station IF Sampling
The CDK2307CILP64's dual matched channels sampling simultaneously at 65-80 MSPS make it well suited to digitizing the intermediate-frequency (IF) outputs of multi-carrier base-station receivers. Each channel acquires one branch of a diversity or sector receiver, and the matched-sample-time architecture preserves the gain and phase relationship required for diversity combining and beamforming. The 12/13-bit resolution comfortably captures the dynamic range of a GSM/EDGE/UMTS/CDMA carrier set with margin for crest-factor peaks, while the CMOS parallel output streams directly into an FPGA for channelization. Power scales with sample rate, so dropping to 20 MSPS during low-traffic periods cuts dissipation for green base-station designs.
推荐
Dual-Channel Video and Imaging Digitizer
The simultaneous-sampling dual-channel architecture of the CDK2307CILP64 captures two synchronized video or imaging streams from RGB/YUV or stereo cameras without requiring two separate ADC parts. At 65-80 MSPS the part digitizes standard HD video rates (148.5 MHz pixel clock) with sample headroom, while 12 or 13-bit resolution preserves color depth above the 8-bit broadcast standard for medical imaging, machine vision, and broadcast equipment. CMOS parallel outputs connect directly to FPGA video pipelines or dual-port video FIFOs, avoiding the latency and complexity of serialized JESD204B interfaces for shorter-distance PCB routes.
推荐
Cable Modem and Set-Top Box Downstream Receiver
The 64-pin QFN dual ADC topology is a good fit for cable-modem downstream tuners and set-top box receivers where IF digitization is followed by digital demodulation in a single host processor. The 65-80 MSPS sampling rates capture DOCSIS/QAM IF bandwidths with margin for adjacent-channel rejection filtering, while 12-13 bits provides enough dynamic range for 256-QAM and below. The internal voltage reference eliminates an external reference chip and the associated drift/lifetime concerns at consumer price points. Operating temperature range must be confirmed against the datasheet for outdoor plant-mounted cable hardware.
推荐
Multi-Channel Test and Measurement Instrumentation
Test instruments such as oscilloscopes, spectrum analyzers, and arbitrary-waveform-generator capture paths benefit from the dual matched channels of the CDK2307CILP64 because gain and phase tracking between channels directly determines amplitude-phase accuracy and image-rejection performance. At 65-80 MSPS the part handles bench-bandwidth channels up to ~30 MHz with margin, and the CMOS parallel output integrates with onboard FPGA DSP blocks for FFT, digital-down-conversion, or trigger derivation. Pairing the dual ADC with a wideband differential front-end amplifier is standard practice to avoid degrading the converter's high analog input bandwidth.
推荐
Ultrasound Beamforming Front End
Medical and industrial ultrasound arrays digitize many channels simultaneously with strict gain/phase tracking; the dual matched channels of the CDK2307CILP64 fit channel-pair layouts where two transducer elements feed one converter IC. The 12/13-bit resolution is well matched to mid-range cart-based ultrasound systems, and 65-80 MSPS per channel comfortably exceeds the 30-40 MSPS needed for 15-20 MHz probe bandwidth. Exposed-pad QFN packaging supports dense PCB layouts with thermal headroom for continuously-operated phased-array probes, while CMOS parallel outputs feed the beamforming ASIC or FPGA with predictable deterministic latency.
推荐
Software-Defined Radio I/Q Digitizer
The two matched ADC channels of the CDK2307CILP64 are well-suited to I/Q baseband sampling in software-defined radios, where one channel captures the I (in-phase) stream and the second captures the Q (quadrature) stream from a quadrature demodulator. Simultaneous sampling ensures the I/Q phase orthogonality is preserved, which is critical for image-rejection performance and low EVM in digital demodulation. At 65-80 MSPS the part handles HF/VHF baseband bandwidths up to ~30 MHz, while the CMOS parallel output fits standard FPGA DSP blocks for downconversion and demodulation pipelines.
推荐
推荐产品汇总
工程参考数据： CDK2307CILP64 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | CDK2307CILP40 | CDK1307CILP40 |
|---|---|---|---|
| Brand | MaxLinear (formerly Exar / Cadeka) | MaxLinear | MaxLinear |
| Package | 64-pin QFN (LP64) | 64-pin QFN (LP64) - same | 64-pin QFN (LP40) - same family footprint |
| Channels | 2 (dual, simultaneous) | 2 (dual, simultaneous) | 2 (dual, simultaneous) |
| Resolution | 12 / 13-bit | 12 / 13-bit | 13-bit fixed |
| Architecture | Pipelined with digital error correction | Pipelined with digital error correction | Pipelined with digital error correction |
| Internal Reference | Yes (on-chip) | Yes (on-chip) | Yes (on-chip) |
| Digital Output | CMOS parallel | CMOS parallel | CMOS parallel |
关键差异点
- Dual matched-channel sampling at 65-80 MSPS in a 64-pin QFN （对比 CDK2307CILP40)
- Selectable 12/13-bit resolution in the same die and package （对比 CDK1307CILP40)
- CMOS parallel digital output for deterministic-latency FPGA interfaces （对比 ADS58C28IRGC25 (LVDS-output dual ADC))
设计说明
Treat the analog and digital grounds as a single low-impedance reference but keep their return-current paths separate on the PCB: route the analog input traces over a contiguous analog ground pour on the top layer, and the CMOS parallel output bus over the digital ground pour. Star-connect both grounds to the exposed pad (EP) of the 64-pin QFN with multiple stitching vias. Place the 100 nF AVDD decoupling capacitors within 2-3 mm of each analog supply pin to suppress switching-current spikes that otherwise couple into the analog input network and degrade SNR.
The dual matched ADC channels of the CDK2307CILP64 rely on identical analog front-end bandwidth and matched trace lengths on each channel to preserve gain and phase tracking. Lay out Channel A and Channel B input traces as length-matched differential pairs (target mismatch <0.5 mm) and use identical termination networks. The CMOS parallel output bus should be series-terminated close to the ADC with 22-33 ohm resistors; with 8-16 simultaneously switching CMOS outputs routing long parallel traces without termination causes ground-bounce and code-dependent channel-to-channel coupling.
Power dissipation on the CDK2307CILP64 scales linearly with sample rate (Estimated: ~1 mW per MSPS per channel at AVDD=3.3V based on typical pipelined-ADC curves), so drop the sample rate to 20 MSPS during standby or receive-only operation to reduce total dissipation. Separate AVDD and DVDD supplies with ferrite beads, and provide a dedicated 1.8V or 3.3V analog LDO upstream of AVDD to reject switching-converter ripple that would otherwise couple into the on-chip reference. Verify the analog input common-mode voltage matches the ADC's input CM range - exceeding it causes signal-dependent distortion not visible in basic DC checks.
Do not float the exposed thermal pad of the 64-pin QFN - it must be soldered to a low-impedance ground pour on the PCB with multiple thermal vias, otherwise both thermal performance and AC linearity degrade. Do not drive the analog inputs single-ended at the rated sample rate - use a wideband differential driver (e.g., a fully-differential op-amp or transformer) to realize the part's full SFDR. Finally, do not assume the internal reference is decoupled internally - add 100 nF plus 10 uF directly at the reference pin to suppress reference-induced conversion spurs.
合规信息
RoHS and lead-free compliance inferred from MaxLinear/Exar/Cadeka standard product lines for LP64 QFN packages; AEC-Q100 automotive qualification is not advertised for this part number. Halogen-free status not explicitly stated in the verified web data.
