CDK2307CILP64 vs CDK1307CILP40 对比
详细并排对比 CDK2307CILP64 出自 MaxLinear 和 CDK1307CILP40 出自 MaxLinear。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | CDK2307CILP64 | CDK1307CILP40 |
|---|---|---|
| 品牌 | MaxLinear | MaxLinear |
| 分类 | ADC/DAC | ADC/DAC |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $5.41 | $3.95 |
| Manufacturer | MaxLinear (formerly Exar / Cadeka) | MaxLinear (formerly Exar/Cadeka) |
| Part Number | CDK2307CILP64 | CDK1307CILP40 |
| 功能 | Dual-channel Analog-to-Digital Converter (ADC) | Analog-to-Digital Converter (ADC) |
| Number of Channels | 2 | — |
| 分辨率 | 12-bit / 13-bit | 12-bit / 13-bit selectable |
| Maximum Sample Rate | 80 MSPS (12-bit), 65 MSPS (13-bit) | — |
| Supported Sample Rates | 20 / 40 / 65 / 80 MSPS | — |
| Converter Architecture | Pipelined with digital error correction | — |
| Input Type | Differential analog inputs | Single-ended analog input |
| Digital Output | Parallel CMOS | — |
| Data Interface | CMOS parallel | — |
| Reference Type | Internal (on-chip) | — |
| 封装 | 64-pin QFN (LP64) with exposed pad | 40-pin LQFP (LP) |
| 安装类型 | Surface Mount | — |
| Packaging | Tray | — |
| 工作温度范围 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | Compliant |
| Sample Rate | — | 65 MSPS (family supports 20/40/65/80 MSPS) |
| Architecture | — | Multi-stage pipeline with digital error correction |
| Full-Scale Input Range | — | 1 Vpp typical |
| Supply Voltage (Analog) | — | 3.3 V |
| Supply Voltage (Digital) | — | 3.3 V |
| Reference | — | Internal (1.2 V bandgap) |
| Output Interface | — | Parallel CMOS |
| Control Interface | — | CMOS serial configuration |
| 工作温度 | — | -40 C to +85 C (industrial) |