EP1810GC-35AB vs EP1810JC-45 对比
详细并排对比 EP1810GC-35AB 出自 Altera 和 EP1810JC-45 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810GC-35AB | EP1810JC-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $21.10 |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | CMOS, UV-erasable |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | — |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| RoHS 状态 | unknown | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Macrocells | — | 48 |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| 最大时钟频率 | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| 封装 | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| 引脚数量 | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |
| 安装类型 | — | Surface Mount |