EP1810GC-35AB vs EP1810JC-45 Comparación
Comparación detallada lado a lado de EP1810GC-35AB por Altera y EP1810JC-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810GC-35AB | EP1810JC-45 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $21,10 |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | CMOS, UV-erasable |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Macrocells | — | 48 |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| Frecuencia de reloj máxima | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Encapsulado | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Recuento de pines | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |
| Tipo de montaje | — | Surface Mount |